Dynamic addressing memory arrays with physical locality

2003 ◽  
Author(s):  
S. Hsu ◽  
Shih-Lien Lu ◽  
Shih-Chang Lai ◽  
R. Krishnamurthy ◽  
K. Lai
Keyword(s):  
Memory Arrays ◽  
Physical Locality

Improving Yield Using Scan and DFT Based Analysis for High Performance PowerPC© Microprocessor

2006 ◽  
Author(s):  
Ray Talacka ◽  
Nandu Tendolkar ◽  
Cynthia Paquette
Keyword(s):  
High Performance ◽  
Yield Enhancement ◽  
Test Time ◽  
Balance Test ◽  
Specific Test ◽  
Defect Location ◽  
Test Methodology ◽  
Memory Arrays ◽  
Scan Chain ◽  
Scan Pattern

Abstract The use of memory arrays to drive yield enhancement has driven the development of many technologies. The uniformity of the arrays allows for easy testing and defect location. Unfortunately, the complexities of the logic circuitry are not represented well in the memory arrays. As technologies push to smaller geometries and the layout and timing of the logic circuitry become more problematic the ability to address yield issue is becoming critical. This paper presents the added yield enhancement capabilities of using e600 core Scan Chain and Scan Pattern testing for logic debug, ways to interpret the fail data, and test methodologies to balance test time and acquiring data. Selecting a specific test methodology and using today's advanced tools like Freescale's DFT/FA has been proven to find more yield issues, earlier, enabling quicker issue resolution.

scholarly journals Workload-aware Electromigration Analysis in Emerging Spintronic Memory Arrays

2021 ◽  
pp. 1-1
Author(s):  
Sarath Mohanachandran Nair ◽  
Mahta Mayahinia ◽  
Mehdi B. Tahoori ◽  
Manu Perumkunnil ◽  
Houman Zahedmanesh ◽  
...  
Keyword(s):  
Memory Arrays

scholarly journals Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays

2007 ◽  
Author(s):  
M. Haykel Ben Jamaa ◽  
David Atienza ◽  
Giovanni De Micheli ◽  
Kirsten E. Moselund ◽  
Didier Bouvet ◽  
...  
Keyword(s):  
Fault Tolerant ◽  
Multi Level ◽  
Memory Arrays

Amorphous silicon memory arrays

2006 ◽  
Vol 352 (9-20) ◽  
pp. 859-862 ◽  
Author(s):  
W.B. Jackson ◽  
R. Elder ◽  
W. Hamburgen ◽  
A. Jeans ◽  
H.-J. Kim ◽  
...  
Keyword(s):  
Amorphous Silicon ◽  
Memory Arrays

scholarly journals Amorphous Metal Oxide Bilayers to Avoid Sneak‐Path Currents for High‐Density Resistive Memory Arrays

2021 ◽  
pp. 2000222
Author(s):  
Shruti Nirantar ◽  
Md Ataur Rahman ◽  
Edwin Mayes ◽  
Madhu Bhaskaran ◽  
Sumeet Walia ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Amorphous Metal ◽  
High Density ◽  
Resistive Memory ◽  
Memory Arrays ◽  
Amorphous Metal Oxide

Address selection by combinatorial decoding of semiconductor memory arrays

1969 ◽  
Vol 4 (5) ◽  
pp. 295-296 ◽  
Author(s):  
F.S. Greene ◽  
W.B. Sander
Keyword(s):  
Semiconductor Memory ◽  
Memory Arrays
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