All-Digital RFID Readers: An RFID Reader Implemented on an FPGA Chip and/or Embedded Processor

2021 ◽  
Vol 22 (3) ◽  
pp. 18-24
Author(s):  
Arnaldo S.R. Oliveira ◽  
Nuno Borges Carvalho ◽  
Joao Santos ◽  
Alirio Boaventura ◽  
Rui Fiel Cordeiro ◽  
...  
Keyword(s):  
Embedded Processor ◽  
Rfid Reader ◽  
Fpga Chip ◽  
Rfid Readers

Design of Pythagorean Hodograph Curve Interpolator Based on NiosII Embedded Processor and FPGA

2011 ◽  
Vol 383-390 ◽  
pp. 6868-6872
Author(s):  
Jing Jie Guo ◽  
Wei Tang
Keyword(s):  
High Speed ◽  
Precision Machining ◽  
Interpolation Algorithm ◽  
Interpolation Scheme ◽  
Embedded Processor ◽  
Computational Burden ◽  
Curve Interpolation ◽  
Pythagorean Hodograph ◽  
Fpga Chip ◽  
Ph Curve

In this paper, a novel architecture of Pythagorean Hodograph (PH) curve interpolator based on Nios Ⅱ embedded processor and FPGA is proposed. The whole interpolator including NiosⅡ processor is built in a single FPGA chip. The interpolator uses a two-stage interpolation scheme to reduce the computational burden of PH curve interpolator. The Nios Ⅱ embedded processor implements 1st-stage interpolation, the FPGA receives the command from the Nios Ⅱ processor and implements 2nd-stage interpolation simultaneously. Therefore, the interpolator can implement the real-time PH curve interpolation algorithm steadily to meet the needs of high-speed and high-precision machining.

Performance Analysis of FPGA Architectures based Embedded Control Applications

2011 ◽  
pp. 274-310 ◽  
Author(s):  
Slim Ben Othman ◽  
Ahmed Karim Ben Salem ◽  
Slim Ben Saoud
Keyword(s):  
Electrical Machine ◽  
Embedded Processor ◽  
Embedded Control ◽  
Digital Devices ◽  
Field Programmable ◽  
Speed Performance ◽  
Fpga Chip ◽  
On Chip ◽  
Machine Drives ◽  
Processor Cores

The performances of System on Chip (SoC) and the Field Programmable Gate Array (FPGA) particularly, are increasing continually. Due to the growing complexity of modern embedded control systems, the need of more performance digital devices is evident. Recent FPGA technology makes it possible to include processor cores into the FPGA chip, which ensures more flexibility for digital controllers. Indeed, greater functionality of hardware and system software, Real-Time (RT) platforms and distributed subsystems are demanded. In this chapter, a design concept of FPGA based controller with Hardware/Software (Hw/Sw) codesign is proposed. It is applied for electrical machine drives. There are discussed different MultiProcessor SoC (MPSoC) architectures with Hw peripherals for the implementation on FPGA-based embedded processor cores. Hw accelerators are considered in the design to enhance the controller speed performance and reduce power consumption. Test and validation of this control system are performed on a RT motor emulator implemented on the same FPGA. Experimental results, carried on a real prototyping platform, are given in order to analyze the performance and efficiency of discussed architecture designs helping to support hard RT constraints.

Design of a novel dual ports antenna to enhance sensitivity of handheld RFID reader

2015 ◽  
Vol 8 (2) ◽  
pp. 369-377 ◽  
Author(s):  
Bo Wang ◽  
Yiqi Zhuang ◽  
Xiaoming Li ◽  
Weifeng Liu
Keyword(s):  
Radio Frequency Identification ◽  
Single Port ◽  
Full Duplex ◽  
Backscatter Signal ◽  
High Isolation ◽  
Rfid Reader ◽  
Space Saving ◽  
Frequency Identification ◽  
Matching Band ◽  
Rfid Readers

A compact dual ports antenna with high isolation is proposed for handheld radio frequency identification (RFID) reader which is rarely reported in open literatures. Different with conventional handheld RFID reader antennas with single port, the proposed antenna transmits and receives signal separately. The proposed antenna operating with full duplex mode can enhance effectively sensitivity of reader, since the strong transmitting signal of reader with single port is usually highly coupled with weak receiving backscatter signal of tag. The antenna utilizes E-shaped aperture-coupled patch structure that occupies less volume and provides further space-saving efficiency. The height of the proposed antenna is only 6.8 mm and the volume of that is 80 mm × 80 mm × 6.8 mm, which is easy to integrate in handheld RFID readers. The antenna uses two E-shaped coupling apertures to excite two orthogonal modes for dual-polarized operation. High isolation of around −30 dB is obtained by proper arrangement of the length of coupling apertures and the position of the stubs. The measured results show −10 dB matching band and −25 dB isolation band from 2.32 to 2.6 GHz and from 2.3 to 2.55 GHz, respectively. The antenna is suitable for applications in handheld RFID readers.

scholarly journals Implement Embedded Controller Using FPGA Chip

2019 ◽  
Vol 8 (2) ◽  
pp. 130
Author(s):  
Haresh Pandya ◽  
Mahesh Rangapariya ◽  
Jitendra Rajput
Keyword(s):  
Embedded Processor ◽  
Standard Requirement ◽  
Embedded Controller ◽  
Fpga Chip

<p>The designer of an FPGA embedded processor system has complete flexibility to select any combination of peripherals and controllers. In fact, the designer can invent new, unique peripherals that can be connected directly to the processor bus. If a designer has a non-standard requirement for a peripheral set, this can be met easily with an FPGA embedded processor system. For example, a designer would not easily find an off-the-shelf processor with ten UARTs. However, in an FPGA, this configuration is very easily accomplished.</p>

scholarly journals A compact miniature fractal planar antenna for RFID readers

2019 ◽  
Vol 15 (1) ◽  
pp. 300 ◽  
Author(s):  
Mohamed Ihamji ◽  
Elhassane Abdelmounim ◽  
Jamal Zbitou ◽  
Hamid Bennis ◽  
Mohamed Latrach
Keyword(s):  
Dielectric Constant ◽  
Radiation Pattern ◽  
Input Impedance ◽  
Microstrip Antenna ◽  
Planar Antenna ◽  
Rfid Reader ◽  
Reader System ◽  
Rfid Readers

<p>This article presents a new miniature microstrip antenna in the ISM "Industrial Scientific and Medical" band, at 2.45 GHz. This microstrip antenna is designed for RFID reader system, by exploiting the fractal technique and the CPW fed; this antenna is printed on FR4 substrate with dielectric constant of 4.4. The validated antenna has a good matching input impedance range from 2.27 GHz to 2.68 GHz with a stable radiation pattern, a gain of 2.2 dBi, and a directivity of 1.91 dB. The total area of the final circuit is 21.22 x 32.05 mm2. A prototype of the proposed antenna has been fabricated and measured.</p>

Embedded Processor-Based Self-Test

2004 ◽  
Author(s):  
Dimitris Gizopoulos ◽  
Antonis Paschalis ◽  
Yervant Zorian
Keyword(s):  
Embedded Processor ◽  
Self Test
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