A fully integrated RFID reader chip targeted to operate in the frequency range of 860 MHz to 960 MHz is designed, simulated and fabricated. To reduce the chip performance degradation due to process and temperature variation, resistor and capacitor calibration is adopted. The output codes of resistor calibration are used to adjust main circuit blocks' biasing current while the output codes of capacitor calibration are used to fine tune filter bandwidth and Digital-to-analog converter (DAC) conversion accuracy. Dual-tuned magnetic coupled LC tanks are also introduced in our VCO design to improve phase noise performance and extend tuning range, so as to enhance the robustness of the proposed RFID reader system. The reader is implemented with a low cost 90 nm standard CMOS process and has a chip area of 3.1 mm by 3.3 mm. The chip is packaged with QFN48 and tested on PCB. The proposed RFID reader consumes 90 mW of power and has robust performance against temperature, voltage supply and process variation. The merits of the chip make it ideal for various application scenarios.
A Low Power Op Amp for 3-Bit Digital to Analog Converter in 0.18 m CMOS Process