New linearization method for low voltage, low power folded cascode LNAs

2012 ◽  
Author(s):  
Mohammad Javad Zavarei ◽  
Ehsan Kargaran ◽  
Hooman Nabovati
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Linearization Method ◽  
Folded Cascode

Novel low-voltage ultra-low-power DVCC based on floating-gate folded cascode OTA

2011 ◽  
Vol 42 (8) ◽  
pp. 1010-1017 ◽  
Author(s):  
Fabian Khateb ◽  
Nabhan Khatib ◽  
Jaroslav Koton
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Floating Gate ◽  
Ultra Low Power ◽  
Folded Cascode

Transconductance enhancement of a low voltage low power recycling folded cascode OTA using an asymmetrical current split input stage

2019 ◽  
Vol 91 ◽  
pp. 53-60
Author(s):  
Amitkumar S. Khade ◽  
Vibha Vyas ◽  
Mukul Sutaone ◽  
Sandeep Musale
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Input Stage ◽  
Folded Cascode

Novel low-voltage low-power high-precision CCII± based on bulk-driven folded cascode OTA

2011 ◽  
Vol 42 (5) ◽  
pp. 622-631 ◽  
Author(s):  
Fabian Khateb ◽  
Nabhan Khatib ◽  
David Kubánek
Keyword(s):  
Low Power ◽  
High Precision ◽  
Low Voltage ◽  
Folded Cascode

Gain increasing techniques for CMOS folded cascode LNAs at low voltage and low power operations

2012 ◽  
Author(s):  
Ehsan Kargaran ◽  
Mohammad Reza Baghbanmanesh ◽  
Mohammad Mahdi Ravari ◽  
Ayub Soltani ◽  
Khalil Mafinezhad ◽  
...  
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Power Operations ◽  
Folded Cascode

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

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