Transconductance enhancement of a low voltage low power recycling folded cascode OTA using an asymmetrical current split input stage

2019 ◽  
Vol 91 ◽  
pp. 53-60
Author(s):  
Amitkumar S. Khade ◽  
Vibha Vyas ◽  
Mukul Sutaone ◽  
Sandeep Musale
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Input Stage ◽  
Folded Cascode

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

Novel low-voltage ultra-low-power DVCC based on floating-gate folded cascode OTA

2011 ◽  
Vol 42 (8) ◽  
pp. 1010-1017 ◽  
Author(s):  
Fabian Khateb ◽  
Nabhan Khatib ◽  
Jaroslav Koton
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Floating Gate ◽  
Ultra Low Power ◽  
Folded Cascode

Novel low-voltage low-power high-precision CCII± based on bulk-driven folded cascode OTA

2011 ◽  
Vol 42 (5) ◽  
pp. 622-631 ◽  
Author(s):  
Fabian Khateb ◽  
Nabhan Khatib ◽  
David Kubánek
Keyword(s):  
Low Power ◽  
High Precision ◽  
Low Voltage ◽  
Folded Cascode

Gain increasing techniques for CMOS folded cascode LNAs at low voltage and low power operations

2012 ◽  
Author(s):  
Ehsan Kargaran ◽  
Mohammad Reza Baghbanmanesh ◽  
Mohammad Mahdi Ravari ◽  
Ayub Soltani ◽  
Khalil Mafinezhad ◽  
...  
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Power Operations ◽  
Folded Cascode

Design of a Low-Voltage Low-Power CMOS Operational Amplifier

2013 ◽  
Vol 380-384 ◽  
pp. 3283-3286
Author(s):  
Lin Hai Cui ◽  
Rui Xu ◽  
Zhan Peng Jiang ◽  
Chang Chun Dong
Keyword(s):  
Low Power ◽  
Operational Amplifier ◽  
High Efficiency ◽  
Low Voltage ◽  
Low Frequency ◽  
Open Loop ◽  
Common Source ◽  
Output Stage ◽  
Input Stage ◽  
Current Mirrors

A low voltage, low power two-stage operational amplifier (op-amp) was proposed in this paper. A folded-cascode structure is used in the input stage of the amplifier to get high gain. Current mirrors are used in the input stage to make the transconduotance constant. A simple push-pull common source amplifier is adopted as the output stage to take the advantages of its high efficiency. The experimental results show that the unity-gain bandwidth is 12.5MHz, the low-frequency open-loop voltage gain is 100dB,the phase margin is 65°, and power dissipation is 98.8μw.

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

Sign in / Sign up

Export Citation Format

Share Document