Ultra-low-voltage robust design issues in deep-submicron CMOS

The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004. ◽

10.1109/newcas.2004.1359013 ◽

2004 ◽

Author(s):

A. Vladimirescu ◽

Yu Cao ◽

O. Thomas ◽

Huifang Qin ◽

D. Markovic ◽

...

Keyword(s):

Robust Design ◽

Low Voltage ◽

Deep Submicron ◽

Design Issues ◽

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Sensing Design Issues in Deep Submicron CMOS SRAMs

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) ◽

10.1109/isvlsi.2005.67 ◽

2005 ◽

Author(s):

A. Natarajan ◽

V. Shankar ◽

A. Maheshwari ◽

W. Burleson

Keyword(s):

Deep Submicron ◽

Design Issues ◽

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Low-Voltage Analog Switch in Deep Submicron CMOS: Design Technique and Experimental Measurements

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1093/ietfec/e89-a.4.1076 ◽

2006 ◽

Vol E89-A (4) ◽

pp. 1076-1087 ◽

Author(s):

C. J. B. FAYOMI

Keyword(s):

Low Voltage ◽

Deep Submicron ◽

Experimental Measurements ◽

Design Technique ◽

Analog Switch ◽

Cmos Design ◽

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A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing ◽

10.1109/tcsii.2007.894428 ◽

2007 ◽

Vol 54 (7) ◽

pp. 586-590 ◽

Author(s):

Suhwan Kim ◽

Stephen V. Kosonocky ◽

Daniel R. Knebel ◽

Kevin Stawiasz ◽

Marios C. Papaefthymiou

Keyword(s):

Low Voltage ◽

Deep Submicron ◽

Power Gating ◽

Submicron Cmos ◽

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1.5 V CMOS bootstrapped dynamic logic circuit techniques (BDLCT) suitable for low-voltage deep-submicron CMOS VLSI for implementing 482 MHz digital quadrature modulator and adder

1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196) ◽

10.1109/icecs.1998.813960 ◽

2002 ◽

Author(s):

J.H. Lou ◽

J.B. Kuo

Keyword(s):

Low Voltage ◽

Dynamic Logic ◽

Deep Submicron ◽

Logic Circuit ◽

Quadrature Modulator ◽

Submicron Cmos ◽

Circuit Techniques ◽

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Low voltage sensing techniques and secondary design issues for sub-90nm caches

ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705) ◽

10.1109/esscirc.2003.1257160 ◽

2004 ◽

Author(s):

M. Sinha ◽

S. Hsu ◽

A. Alvandpour ◽

W. Burleson ◽

R. Krishnamurthy ◽

...

Keyword(s):

Low Voltage ◽

Design Issues ◽

Voltage Sensing

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Performance and reliability aspects of FOND: a new deep submicron CMOS device concept

IEEE Transactions on Electron Devices ◽

10.1109/16.535326 ◽

1996 ◽

Vol 43 (9) ◽

pp. 1407-1415 ◽

Author(s):

R. Bellens ◽

G. Van den Bosch ◽

P. Habas ◽

J.-P. Mieville ◽

G. Badenes ◽

...

Keyword(s):

Deep Submicron ◽

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Equivalent circuit models for stacked spiral inductors in deep submicron CMOS technology

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. ◽

10.1109/iscas.2003.1205682 ◽

2003 ◽

Author(s):

S.C. Rustagi ◽

Chun-Geik Tan

Keyword(s):

Equivalent Circuit ◽

Cmos Technology ◽

Deep Submicron ◽

Spiral Inductors ◽

Submicron Cmos ◽

Equivalent Circuit Models

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Bridging fault modeling and simulation for deep submicron CMOS ICs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2002.800457 ◽

2002 ◽

Vol 21 (8) ◽

pp. 941-953 ◽

Author(s):

M. Favalli ◽

M. Dalpasso

Keyword(s):

Modeling And Simulation ◽

Fault Modeling ◽

Deep Submicron ◽

Bridging Fault ◽

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TECHNOLOGY ROADMAP CHALLENGES FOR DEEP SUBMICRON CMOS

Microelectronics, Microsystems and Nanotechnology ◽

10.1142/9789812810861_0021 ◽

2001 ◽

Author(s):

C. L. CLAEYS ◽

H. E. MAES

Keyword(s):

Deep Submicron ◽

Technology Roadmap ◽

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Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in submicron CMOS technology

IEEE Transactions on Electron Devices ◽

10.1109/16.662790 ◽

1998 ◽

Vol 45 (4) ◽

pp. 849-860 ◽

Author(s):

Ming-Dou Ker

Keyword(s):

Low Voltage ◽

Cmos Technology ◽

High Current ◽

Esd Protection ◽

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