Linearity Improvement of Bulk Driven Floating Gate OTA Using Cross-Bulk and Quasi-Bulk Techniques

In this paper, two highly linear OTAs are presented using a combination of three linearization techniques: floating gate, bulk driven, and source degeneration. In the first OTA, bulk driven floating gate MOSFETs are used as input transistors. The input signal given at the bulk terminals of these input transistors are in the opposite phase of the input signal provided to one of the gates of the respective floating gate MOSFET. This cross-coupling method resulted in a highly linear voltage-to-current conversion at the cost of reduced transconductance. In the second proposed OTA, this reduction in transconductance is restored by using novel quasi-bulk floating gate MOSFETs as input transistors while maintaining the improved linearity. Both the OTAs are designed and simulated using 180 nm CMOS design library and powered with [Formula: see text]0.5[Formula: see text]V dual power supply. The process variation and mismatch effects on both the OTAs are examined using corner and Monte Carlo analysis. The layouts of the proposed OTAs are also presented and workability is confirmed using post-layout simulations.

Frequency-Compensated Bulk-Driven TIA Suitable for Low-Voltage Low-Power Applications

The importance of a transimpedance amplifier in an optical transceiver is very well known. In this paper, a novel CMOS design of the bulk-driven transimpedance amplifier (BD-TIA) is given where the bridge-shunt peaking-based frequency compensation technique is exploited to improve frequency response. A pre-existing active inductor has been used for the same. The electrical characteristics and functioning of this inductor simulator make it a suitable alternative to both floating and grounded spiral inductors. In order to verify the workability of the proposed circuit, it has been simulated with TSMC CMOS 0.18[Formula: see text][Formula: see text]m process parameters. The proposed circuit is useful in low-voltage low-power VLSI applications as it uses a single supply of 0.75[Formula: see text]V. The power consumption of BD-TIA is very low, being 0.37[Formula: see text]mW, because a standard MOSFET has been replaced by a bulk-driven MOSFET (BDMOS), while the 3-dB bandwidth is observed to be 4.5[Formula: see text]GHz. The mathematical investigation and small signal analysis show that the simulation results are in good agreement.

A Compact Four Transistor CMOS-Design of a Floating Memristor for Adaptive Spiking Neural Networks and Corresponding Self-X Sensor Electronics to Industry 4.0

In this work we present, in the context of the transition from amplitude to robust spike domain sensing and electronics, a floating memristor. It can be used to construct memristor SNNs used for noise-robust conditioning and analog-to-digital conversion and manufactured using leading-edge technologies with more ’cranky’ devices, low-voltage, low power, and minimal area on-chip. Also, this supports both machine learning as well as the self-x properties in advanced sensor electronics system for industry 4.0. The proposed memristor has less design complexity and a higher number of resistance levels as compared to other existing memristors. The proposed CMOS memristor is designed using AMS 0.35 μm CMOS technology and Cadence design tools. Its layout occupies an area of 70 μm × 85 μm. The simulation shows the performance of the proposed floating memristor emulator in the temperature range (-40 °C to 85 °C) and Monte-Carlo simulation.

Design and Implementation of Low-Power, High-Performance 2-4- and 4-16-Line Decoders using Adiabatic Logic Circuits

In the present emerging field for the research, the reduction of power has become a major design problem in VLSI technology. As the size of the system shrinking gradually it has become the one the prime concerns in the design of decoders. The main purpose of this paper is to minimize the power and delay capabilities comparison with ordinary CMOS design. To avoid power reduction by introducing a different technique. In this paper we are approaching the adiabatic circuit has been introduced. The power dissipation in the adiabatic circuits can be minimized when compared to conventional CMOS logic. The designing of decoders with the adiabatic logic can reduce the power average power by 10.80% and delay by 21%, 23% and 24% at different voltage levels compared to the conventional CMOS. Finally, Spice simulation results show the comparison results between the existing CMOS decoders and the proposed adiabatic logic-based decoders at 32nm technology in all cases.

Telescopic Ota Based Cmos Design of High Gain, High Cmrr, Larger Bandwidth Instrumentation Amplifier

Instrumentation amplifiers (IA) play a crucial role wherever small differential voltages need to be amplified precisely in the occurrence of a any voltage at the input. It must therefore attribute high input-impedance, small input-referred noise and offset voltage, large differential-voltage gain without feedback and significantly cast-off deviations on power-supply and common mode voltages. In this paper efficient instrumentation amplifier with high gain, high CMRR and larger bandwidth is implemented. The proposed differential amplifier may be used for various control systems as well as small signal conditioning circuits; instrumentation amplifier having larger product of gain and bandwidth would encounter maximum application in these desires.