Design parameters of dispersion decreasing fiber based OTDM source: quasi-adiabatic higher-order soliton compression from sinusoidal input signal

2002 ◽  
Author(s):  
Duckey Lee ◽  
Na Young Kim ◽  
Kyoung Min Kim ◽  
Namkyoo Park ◽  
Seong Joon Ahn ◽  
...  
Keyword(s):  
Input Signal ◽  
Higher Order ◽  
Design Parameters ◽  
Sinusoidal Input ◽  
Soliton Compression

Effect of Distributed Attached Mass on the Vibration of Sandwich Panel Using Higher Order ESL Theory

2012 ◽  
Vol 488-489 ◽  
pp. 35-39 ◽  
Author(s):  
Shahab Tafazoli ◽  
S.M.R. Khalili
Keyword(s):  
Free Vibration ◽  
Natural Frequency ◽  
Material Properties ◽  
Sandwich Panel ◽  
Sandwich Panels ◽  
Single Layer ◽  
Higher Order ◽  
Design Parameters ◽  
Attached Mass ◽  
The Face

In this paper, effects of adding a distributed attached mass added to the face sheets of sandwich panels on free vibration of the system are investigated. Higher order equivalent single layer (ESL) theory is expanded and used. Mass Inertias of the distributed attached mass are taking into account. Various design parameters including geometrical and material properties, such as density, thickness of the attached mass and the panel are investigated to show the decreasing effect on the fundamental natural frequency of the system due to the adding of the distributed attached mass.

MAPPING DISCRETE-TIME MODELS FOR DESCRIPTOR-SYSTEMS WITH CONSISTENT INITIAL CONDITIONS

2016 ◽  
Vol 40 (1) ◽  
pp. 59-77 ◽  
Author(s):  
Shin Kawai ◽  
Noriyuki Hori
Keyword(s):  
Discrete Time ◽  
Continuous Time ◽  
Initial Conditions ◽  
Descriptor Systems ◽  
Descriptor System ◽  
Initial Time ◽  
Design Parameters ◽  
Time Model ◽  
Discrete Time Model ◽  
Sinusoidal Input

Discretization of a regular continuous-time descriptor-system, whose initial condition is consistent with its input, is considered using a general mapping method presented in our previous paper. The proposed mapping discrete-time model is shown to be a proper discretization under the definition explained in the paper. This assures that the response of the mapping model approaches that of the continuous-time descriptor system as the sampling period approaches zero. The consistency of initial conditions for the discrete-time model is also studied and the long-standing issue of ambiguities surrounding irregularities of discrete-time responses at the initial time are clarified with a simple solution. A proper range of design parameters are investigated and their suitable choices suggested. To illustrate the use of the proposed method, a simple circuit that cannot be expressed in the ordinary state-space form is considered. Its responses to a sinusoidal input when started from the consistent and inconsistent initial conditions are simulated to show that the irregularities at the initial time can be overcome easily. The proposed technique provides a convenient simulation and design environment for handling discrete-time systems in a unified manner with consistency and ease.

A Simple and Efficient Charge Injection Error Compensation Structure for MOS Sampling Switches

2018 ◽  
Vol 27 (08) ◽  
pp. 1850130 ◽  
Author(s):  
Saeed Naghavi ◽  
Mojde Nematzade ◽  
Niloofar Sharifi ◽  
Tohid Moradi Khanshan ◽  
Adib Abrishamifar ◽  
...  
Keyword(s):  
Input Signal ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Charge Injection ◽  
Sampled Data ◽  
Sampling Errors ◽  
Wide Range ◽  
Sinusoidal Input ◽  
Simulation Results

This paper introduces a new technique to design an analog MOS switch to be used in sampled-data circuits. In any sampled-data system, the accuracy of the sampling switch is a critical parameter to determine the overall performance of the system. To satisfy accuracy requirements of the switch, a novel technique to reduce channel charge injection error is proposed. The proposed switch has a very simple structure and it uses a small area of the chip. Also, it has a low on-resistance and its variation over the input signal range is acceptable. In order to evaluate the performance of the proposed switch, simulations are done in a 0.18[Formula: see text][Formula: see text]m standard CMOS technology. Simulation results show that the sampling errors produced by the channel charge injection is eliminated through a cancellation technique using an auxiliary transistor. The output error charge due to charge injection over a wide range of the input signal variation is very low (less than 1.45[Formula: see text]fC). Also, simulation results show that the proposed switch achieves signal-to-noise plus distortion ratio (SNDR) of 85.05[Formula: see text]dB, effective number of bits (ENOB) of 13.83, total harmonic distortion (THD) of [Formula: see text]87.23[Formula: see text]dB and spurious-free dynamic range (SFDR) of 88.14[Formula: see text]dB for a 1[Formula: see text]MHz sinusoidal input of 800[Formula: see text]mV peak-to-peak amplitude at 50[Formula: see text]MHz sampling rate with a 1.8[Formula: see text]V supply voltage.

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