A Simple and Efficient Charge Injection Error Compensation Structure for MOS Sampling Switches

2018 ◽  
Vol 27 (08) ◽  
pp. 1850130 ◽  
Author(s):  
Saeed Naghavi ◽  
Mojde Nematzade ◽  
Niloofar Sharifi ◽  
Tohid Moradi Khanshan ◽  
Adib Abrishamifar ◽  
...  
Keyword(s):  
Input Signal ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Charge Injection ◽  
Sampled Data ◽  
Sampling Errors ◽  
Wide Range ◽  
Sinusoidal Input ◽  
Simulation Results

This paper introduces a new technique to design an analog MOS switch to be used in sampled-data circuits. In any sampled-data system, the accuracy of the sampling switch is a critical parameter to determine the overall performance of the system. To satisfy accuracy requirements of the switch, a novel technique to reduce channel charge injection error is proposed. The proposed switch has a very simple structure and it uses a small area of the chip. Also, it has a low on-resistance and its variation over the input signal range is acceptable. In order to evaluate the performance of the proposed switch, simulations are done in a 0.18[Formula: see text][Formula: see text]m standard CMOS technology. Simulation results show that the sampling errors produced by the channel charge injection is eliminated through a cancellation technique using an auxiliary transistor. The output error charge due to charge injection over a wide range of the input signal variation is very low (less than 1.45[Formula: see text]fC). Also, simulation results show that the proposed switch achieves signal-to-noise plus distortion ratio (SNDR) of 85.05[Formula: see text]dB, effective number of bits (ENOB) of 13.83, total harmonic distortion (THD) of [Formula: see text]87.23[Formula: see text]dB and spurious-free dynamic range (SFDR) of 88.14[Formula: see text]dB for a 1[Formula: see text]MHz sinusoidal input of 800[Formula: see text]mV peak-to-peak amplitude at 50[Formula: see text]MHz sampling rate with a 1.8[Formula: see text]V supply voltage.

Area-Efficient Capacitor-Splitting Switching Scheme with a Nearly Constant Common-Mode Voltage for SAR ADCs

2019 ◽  
Vol 29 (10) ◽  
pp. 2020005
Author(s):  
Hao Wang ◽  
Wenming Xie ◽  
Zhixin Chen
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Switching Scheme ◽  
Common Mode ◽  
Analog To Digital ◽  
Common Mode Voltage ◽  
Switching Method ◽  
Area Efficient

A novel area-efficient switching scheme is proposed for the successive approximation register (SAR) analog-to-digital converters (ADCs). The capacitor-splitting structure, charge-average switching technique, and [Formula: see text] (equal to [Formula: see text]/4) are combined together and optimized to realize the proposed switching scheme. [Formula: see text] is only used in the last two bit cycles, which affects the ADC accuracy little and reduces capacitor area by half. It achieves a 98% less switching energy and an 87.5% less capacitor area compared with the conventional switching method. In addition, the DAC output common-mode voltage is approximately constant. Thus, the proposed switching method is a good tradeoff among power consumption, capacitor area, DAC output common-mode voltage, and ADC accuracy. The proposed SAR ADC is simulated in 0.18[Formula: see text][Formula: see text]m CMOS technology with a supply voltage of 0.6[Formula: see text]V and at a sampling rate of 20[Formula: see text]kS/s. The signal-to-noise-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 58.2 and 73.7[Formula: see text]dB, respectively. The effective number of bits (ENOB) is 9.4. It consumes 42[Formula: see text]nW, resulting in a figure-of-merit (FoM) of 3.11 fJ/conversion-step.

scholarly journals A Controllable Constant Power Generator in 0.35 μm CMOS Technology for Thermal-Based Sensor Applications

2018 ◽  
Vol 2018 ◽  
pp. 1-12
Author(s):  
Milena Zogović Erceg
Keyword(s):  
Relative Error ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Load Resistance ◽  
Cmos Technology ◽  
Constant Power ◽  
Power Generator ◽  
Sensor Applications ◽  
Wide Range ◽  
Resistive Loads

A CMOS controllable constant power generator based on multiplier/divider circuit is presented. It generates constant power for a wide range of the resistive loads. For the generated power of 5 mW, and the resistance range from 0.5 kΩ to 1.5 kΩ, the relative error of dissipated power is less than 0.6%. For single supply voltage of 5 V, presented controllable constant power generator generates power from 0.5 mW to 7.8 mW, for the load resistance dynamic range from 3 up to 15, while the relative error of generated power is less than 2%. The frequency bandwidth of the proposed design is up to 5 MHz. Through the detailed analysis of the loop gain, it is shown that the circuit has no stability problems.

scholarly journals RESEARCH PROCESSES OF GAMMA RADIATION DETECTOR FOR DEVELOPING A PORTABLE DIGITAL SPECTROMETER

2020 ◽  
pp. 5-12 ◽  
Author(s):  
O.V. Banzak ◽  
O.V. Sieliykov ◽  
M.V. Olenev ◽  
S.V. Dobrovolskaya ◽  
O.I. Konovalenko
Keyword(s):  
Gamma Radiation ◽  
Dose Rate ◽  
Power Plants ◽  
Gamma Ray ◽  
Dynamic Range ◽  
Radiation Detector ◽  
Minimum Energy ◽  
Sampling Rate ◽  
Nuclear Materials ◽  
Wide Range

When considering methods of combating the illicit circulation of nuclear materials, it is necessary to detect trace amounts of materials, and in many cases not to seize them immediately, but to establish the place of storage, processing, routes of movement, etc. As a result, there is a new demand for isotope identification measurements to meet a wide range of different requirements. Measurements should be carried out in the field in a short time, when results need to be obtained within tens of seconds. The devices with which the personnel work should be small and low-background. Such requirements appear when working to identify cases of illegal trade in nuclear materials and radioactive sources, as well as when solving radiation protection problems and when handling radioactive devices and waste. In this work, new generation radiation sensors and measuring systems based on them have been created, which open up previously unknown possibilities in solving problems of nuclear fuel analysis, increasing the accuracy and efficiency of monitoring technological parameters and the state of protective barriers in nuclear power plants, and creating means for IAEA inspections. For the first time a portable digital gamma-ray spectrometer for radiation reconnaissance in the field was developed and created. Distinctive features of such devices are: The analysis showed that the required value of error due to energy dependence of the sensitivity can be achieved using, for example, Analog Devices 10-bit AD9411 ADCs with a sampling rate of 170 MHz. The number of quantization levels is determined by the requirement to measure the dose rate of gamma radiation with an energy of at least 10 keV. This minimum energy corresponds to the use of 10-bit ADCs. On the basis of the developed model, an ionizing radiation detector for dosimetry was created. Its fundamental difference from known devices is the use of CdZnTe crystals as a primary gamma-ray converter (sensor). The advantages of such a solution, proved by previous studies, made it possible to create a detector with: high resolution, no more than 40 keV; a wider dynamic range of values of the recorded radiation dose rate - from background to emergency operating modes of the reactor; lower value of the energy equivalent of noise.

scholarly journals A Switched-MOSFET Programmable Low-Voltage Filter

2004 ◽  
Vol 1 (1) ◽  
pp. 32-37
Author(s):  
Luís Cléber C. Marques ◽  
Wouter A. Serdijn
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Total Current ◽  
Sampled Data ◽  
Current Consumption ◽  
Digitally Programmable ◽  
Low Supply Voltage

This paper describes a digitally programmable low-voltage low-power analogue filter that can be used in hearing-aid circuits. The filter employs the recently introduced switched-MOSFET technique, a sampled-data technique suitable for low supply voltage operation since it avoids the conduction gap of the switches and does not need any dedicated process. The filter was implemented using the DIMES 1.6μm CMOS process and achieves 64 dB dynamic range. The total current consumption, drawn from a 2.2V supply, equals 93μA.

scholarly journals A Power-Efficient Pipelined ADC with an Inherent Linear 1-Bit Flip-Around DAC

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 199 ◽  
Author(s):  
Peiyuan Wan ◽  
Limei Su ◽  
Hongda Zhang ◽  
Zhijie Chen
Keyword(s):  
Dynamic Range ◽  
Low Voltage ◽  
Sampling Rate ◽  
Measured Signal ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Least Significant Bit ◽  
Power Efficient ◽  
Sinusoidal Input ◽  
Bit Flip

An unity-gain 1-bit flip-around digital-to-analog converter (FADAC), without any capacitor matching issue, is proposed as the front-end input stage in a pipelined analog-to-digital converter (ADC), allowing an input signal voltage swing up to be doubled. This large input swing, coupled with the inherent large feedback factor (ideally β = 1) of the proposed FADAC, enables a power-efficient low-voltage high-resolution pipelined ADC design. The 1-bit FADAC is exploited in a SHA-less and opamp-sharing pipelined ADC, exhibiting 12-bit resolution with an input swing of 1.8 Vpp under a 1.1 V power supply. Fabricated in a 0.13-μm CMOS process, the prototype ADC achieves a measured signal-to-noise plus distortion ratio (SNDR) of 66.4 dB and a spurious-free dynamic range (SFDR) of 76.7 dB at 20 MS/s sampling rate. The ADC dissipates 5.2 mW of power and occupies an active area of 0.44 mm2. The measured differential nonlinearity (DNL) is +0.72/−0.52 least significant bit (LSB) and integral nonlinearity (INL) is +0.84/−0.75 LSB at a 3-MHz sinusoidal input.

A 0.6V 19.5μW 80dB DR ΔΣ Modulator with SA-Quantizers and Digital Feedforward Path

2017 ◽  
Vol 26 (07) ◽  
pp. 1750117 ◽  
Author(s):  
Hongmei Chen ◽  
Li Wang ◽  
Ting Li ◽  
Lin He ◽  
Fujiang Lin
Keyword(s):  
Input Signal ◽  
Dynamic Range ◽  
Low Voltage ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Dynamic Element Matching ◽  
Loop Filter ◽  
Op Amp ◽  
Low Voltage Operation ◽  
Delta Sigma

This paper presents a discrete-time multi-bit Delta–Sigma modulator employing successive approximation (SA)-quantizers for bio-signal acquisitions. In the proposed [Formula: see text] modulator, the input signal is separately quantized and the signal summation is performed in the digital domain to avoid the power hungry analog adder. Two SA-quantizers are used in this modulator. One is dedicated to quantize the input signal and the other is to quantize the summation of the integrators’ outputs. Dynamic Element Matching (DEM) technique is used to mitigate the mismatch among the digital-to-analog conversion (DAC) elements. To reduce the complexity of the DEM logic, the 7-bit summed quantizer output is truncated into a 5-bit code before it is fed to the DEM circuits. Double tailed inverter-based op-amp is used in the loop filter for low-voltage operation. Correlated-double-sampling is adopted to enhance the effective gain of the integrator. The proposed modulator is designed and fabricated in a 130-nm CMOS technology. The measurement result shows that the modulator achieves a dynamic range of 80[Formula: see text]dB, a peak SNDR of 77[Formula: see text]dB in a 25[Formula: see text]kHz signal bandwidth at sampling rate of 800[Formula: see text]kHz. The prototype modulator occupies 0.25[Formula: see text]mm2 and consumes only 19.5[Formula: see text][Formula: see text]W from a 0.6[Formula: see text]V supply. The proposed modulator achieves a figure of merit of 67 fJ per conversion step.

A Novel MIM-Capacitor-Based 1-GS/s 14-bit Variation-Tolerant Fully-Differential Voltage-to-Time Converter (VTC) Circuit

2017 ◽  
Vol 26 (05) ◽  
pp. 1750073
Author(s):  
Abdullah El-Bayoumi ◽  
Hassan Mostafa ◽  
Ahmed M. Soliman
Keyword(s):  
Software Defined Radio ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Digital Converter ◽  
Pulse Delay ◽  
Fully Differential ◽  
Metal Insulator Metal ◽  
Simulation Results

Time-based Analog-to-Digital Converter (TADC), plays a major role in designing Software-Defined Radio (SDR) receivers, at scaled CMOS technologies, as it manifests lower area and power than conventional ADCs. TADC consists of 2 major blocks. The input voltage is converted into a pulse delay using a Voltage-to-Time Converter (VTC). In additions, the pulse delay is converted into a digital word using a Time-to-Digital Converter (TDC). In this paper, a novel fully-differential VTC based on a new methodology is presented which reports a highly-linear design. A metal-insulator-metal (MIM) capacitor as well as a dynamic calibration technique based on a set of large-sized capacitor-based voltage dividers circuits are utilized to automatically compensate the Process-Voltage-Temperature (PVT) variations. Moreover, the layout design is introduced. The proposed design operates on a 1[Formula: see text]GS/s sampling frequency with a supply voltage of 1.2[Formula: see text]V. After calibration, simulation results, using TSMC 65[Formula: see text]nm CMOS technology, report a 1.42[Formula: see text]V wider dynamic range due to the differential mechanism with a 3% linearity error. This design achieves a resolution up to 14 bits, a 0.07 fJ/conversion FOM, a 229[Formula: see text][Formula: see text]m2 area and a 0.25[Formula: see text]mW power. The simulation results are compared to the single-ended VTC results and the state-of-the-art analog-part ADCs results to show the strength of the proposed design.

A Circuit for Robustness Enhancement of the Subthreshold SRAM Bitcell in 65nm Technology

2012 ◽  
Vol 542-543 ◽  
pp. 1001-1006
Author(s):  
Bai Tao Lv ◽  
Rui Xing Li ◽  
Jiafeng Zhu ◽  
Na Bai ◽  
Xiu Long Wu
Keyword(s):  
Threshold Voltage ◽  
Supply Voltage ◽  
The Body ◽  
Mean Values ◽  
Noise Margin ◽  
Wide Range ◽  
Standard Values ◽  
The Mean ◽  
Simulation Results ◽  
Static Noise

This paper describes a circuit which can enhance the robustness of the subthreshold 6T SRAM bitcell. The proposed circuit can dynamically adjust the body voltages of the PMOS transistors in order to enhance the robustness of the subthreshold 6T SRAM bitcell by detecting the variation of the threshold voltage. The simulation results under 300mV in 65nm technology demonstrate that the mean values of the read and hold static noise margin (SNM) of the subthreshold 6T SRAM bitcell have been improved by 18% and 0.7%, respectively, meanwhile the standard values of the read and hold SNM have improved by 82% and 29.4%, respectively, by adopting the proposed circuit. Moreover, the proposed circuit functions well in a wide range of supply voltage from 0.2V to 0.5V.

The Attenuation of Very Low Frequency Brain Oscillations in Transitions from a Rest State to Active Attention

2009 ◽  
Vol 23 (4) ◽  
pp. 191-198 ◽  
Author(s):  
Suzannah K. Helps ◽  
Samantha J. Broyd ◽  
Christopher J. James ◽  
Anke Karl ◽  
Edmund J. S. Sonuga-Barke
Keyword(s):  
Brain Activity ◽  
Sampling Rate ◽  
Low Frequency ◽  
Future Research ◽  
Adhd Symptoms ◽  
Default Mode ◽  
Very Low Frequency ◽  
Wide Range ◽  
Interference Hypothesis ◽  
Mode Interference

Background: The default mode interference hypothesis ( Sonuga-Barke & Castellanos, 2007 ) predicts (1) the attenuation of very low frequency oscillations (VLFO; e.g., .05 Hz) in brain activity within the default mode network during the transition from rest to task, and (2) that failures to attenuate in this way will lead to an increased likelihood of periodic attention lapses that are synchronized to the VLFO pattern. Here, we tested these predictions using DC-EEG recordings within and outside of a previously identified network of electrode locations hypothesized to reflect DMN activity (i.e., S3 network; Helps et al., 2008 ). Method: 24 young adults (mean age 22.3 years; 8 male), sampled to include a wide range of ADHD symptoms, took part in a study of rest to task transitions. Two conditions were compared: 5 min of rest (eyes open) and a 10-min simple 2-choice RT task with a relatively high sampling rate (ISI 1 s). DC-EEG was recorded during both conditions, and the low-frequency spectrum was decomposed and measures of the power within specific bands extracted. Results: Shift from rest to task led to an attenuation of VLFO activity within the S3 network which was inversely associated with ADHD symptoms. RT during task also showed a VLFO signature. During task there was a small but significant degree of synchronization between EEG and RT in the VLFO band. Attenuators showed a lower degree of synchrony than nonattenuators. Discussion: The results provide some initial EEG-based support for the default mode interference hypothesis and suggest that failure to attenuate VLFO in the S3 network is associated with higher synchrony between low-frequency brain activity and RT fluctuations during a simple RT task. Although significant, the effects were small and future research should employ tasks with a higher sampling rate to increase the possibility of extracting robust and stable signals.

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