Implementation of a level 1 trigger system using high speed serial (VXS) techniques for the 12GeV high luminosity experimental programs at Thomas Jefferson National Accelerator Facility

Author(s):  
C. Cuevas ◽  
B. Raydo ◽  
H. Dong ◽  
A. Gupta ◽  
F. J. Barbosa ◽  
...  
2020 ◽  
Vol 2020 (8) ◽  
Author(s):  
Biplob Bhattacherjee ◽  
Swagata Mukherjee ◽  
Rhitaja Sengupta ◽  
Prabhat Solanki

Abstract Triggering long-lived particles (LLPs) at the first stage of the trigger system is very crucial in LLP searches to ensure that we do not miss them at the very beginning. The future High Luminosity runs of the Large Hadron Collider will have increased number of pile-up events per bunch crossing. There will be major upgrades in hardware, firmware and software sides, like tracking at level-1 (L1). The L1 trigger menu will also be modified to cope with pile-up and maintain the sensitivity to physics processes. In our study we found that the usual level-1 triggers, mostly meant for triggering prompt particles, will not be very efficient for LLP searches in the 140 pile-up environment of HL-LHC, thus pointing to the need to include dedicated L1 triggers in the menu for LLPs. We consider the decay of the LLP into jets and develop dedicated jet triggers using the track information at L1 to select LLP events. We show in our work that these triggers give promising results in identifying LLP events with moderate trigger rates.


2018 ◽  
Vol 182 ◽  
pp. 02037
Author(s):  
Silvio Donato

During its second run of operation (Run 2), started in 2015, the LHC will deliver a peak instantaneous luminosity that may reach 2 · 1034 cm-2s-1 with an average pileup of about 55, far larger than the design value. Under these conditions, the online event selection is a very challenging task. In CMS, it is realized by a two-level trigger system: the Level-1 (L1) Trigger, implemented in custom-designed electronics, and the High Level Trigger (HLT), a streamlined version of the offine reconstruction software running on a computer farm. In order to face this challenge, the L1 trigger has been through a major upgrade compared to Run 1, whereby all electronic boards of the system have been replaced, allowing more sophisticated algorithms to be run online. Its last stage, the global trigger, is now able to perform complex selections and to compute high-level quantities, like invariant masses. Likewise, the algorithms that run in the HLT have been greatly improved; in particular, new approaches for the online track reconstruction lead to a drastic reduction of the computing time, and to much improved performances. This document will describe the performance of the upgraded trigger system in Run 2.


Author(s):  
R. Achenbach ◽  
P. Adragna ◽  
V. Andrei ◽  
B.M. Barnett ◽  
B. Bauss ◽  
...  
Keyword(s):  

2005 ◽  
Vol 52 (4) ◽  
pp. 1217-1222 ◽  
Author(s):  
P.B. Amaral ◽  
N. Ellis ◽  
P. Farthouat ◽  
P. Gallno ◽  
J. Haller ◽  
...  
Keyword(s):  

Author(s):  
Jinyuan Wu ◽  
M. Wang ◽  
E. Gottschalk ◽  
D. Christian ◽  
X. Li ◽  
...  
Keyword(s):  

2019 ◽  
Vol 214 ◽  
pp. 01034
Author(s):  
Ralf Spiwoks ◽  
Aaron Armbruster ◽  
German Carrillo-Montoya ◽  
Magda Chelstowska ◽  
Patrick Czodrowski ◽  
...  

The Muon to Central Trigger Processor Interface (MUCTPI) of the ATLAS experiment at the Large Hadron Collider(LHC) at CERN is being upgraded for the next run of the LHC in order to use optical inputs and to provide full-precision information for muon candidates to the topological trigger processor (L1TOPO) of the Level-1 trigger system. The new MUCTPI is implemented as a single ATCA blade with high-end processing FPGAs which eliminate doublecounting of muon candidates in overlapping regions, send muon candidates to L1TOPO, and muon multiplicities tothe Central Trigger Processor (CTP), as well as readout data to the data acquisition system of the experiment. A Xilinx Zynq System-on-Chip (SoC) with a programmable logic part and a processor part is used for the communication to the processing FPGAs and the run control system. The processor part, based on ARM processor cores, is running embedded Linux prepared using the framework of the Linux Foundation's Yocto project. The ATLAS run control software was ported to the processor part and a run control application was developed which receives, at configuration, all data necessary for the overlap handling and candidate counting of the processing FPGAs. During running, the application provides ample monitoring of the physics data and of the operation of the hardware. *


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