A 2 mW, 55.8-GHz CMOS injection-locked frequency divider with 7.1-GHz locking range

2009 ◽  
Author(s):  
Wei-Lun Hsu ◽  
Chang-Zhi Chen ◽  
Yo-Sheng Lin ◽  
Chi-Chen Chen
Keyword(s):  
Frequency Divider ◽  
Locking Range

scholarly journals An 18.8–33.9 GHz, 2.26 mW Current-Reuse Injection-Locked Frequency Divider for Radar Sensor Applications

Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2551
Author(s):  
Kwang-Il Oh ◽  
Goo-Han Ko ◽  
Jeong-Geun Kim ◽  
Donghyun Baek
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Frequency Divider ◽  
Oxide Semiconductor ◽  
Center Frequency ◽  
Radar Sensor ◽  
Frequency Locking ◽  
Current Reuse ◽  
Sensor Applications ◽  
Locking Range

An 18.8–33.9 GHz, 2.26 mW current-reuse (CR) injection-locked frequency divider (ILFD) for radar sensor applications is presented in this paper. A fourth-order resonator is designed using a transformer with a distributed inductor for wideband operating of the ILFD. The CR core is employed to reduce the power consumption compared to conventional cross-coupled pair ILFDs. The targeted input center frequency is 24 GHz for radar application. The self-oscillated frequency of the proposed CR-ILFD is 14.08 GHz. The input frequency locking range is from 18.8 to 33.8 GHz (57%) at an injection power of 0 dBm without a capacitor bank or varactors. The proposed CR-ILFD consumes 2.26 mW of power from a 1 V supply voltage. The entire die size is 0.75 mm × 0.45 mm. This CR-ILFD is implemented in a 65 nm complementary metal-oxide semiconductor (CMOS) technology.

A Low Power V-Band CMOS Frequency Divider With Wide Locking Range and Accurate Quadrature Output Phases

2008 ◽  
Vol 43 (4) ◽  
pp. 991-998 ◽  
Author(s):  
Qun Gu ◽  
Zhiwei Xu ◽  
Daquan Huang ◽  
Tim LaRocca ◽  
Ning-Yi Wang ◽  
...  
Keyword(s):  
Low Power ◽  
Frequency Divider ◽  
V Band ◽  
Locking Range ◽  
Wide Locking Range

scholarly journals A Reference-Sampling Based Calibration-Free Fractional-N PLL with A PI-Linked Sampling Clock Generator

Sensors ◽  
2021 ◽  
Vol 21 (20) ◽  
pp. 6824
Author(s):  
Jae-Soub Han ◽  
Tae-Hyeok Eom ◽  
Seong-Wook Choi ◽  
Kiho Seong ◽  
Dong-Hyun Yoon ◽  
...  
Keyword(s):  
Random Sequence ◽  
Reference Signal ◽  
Frequency Divider ◽  
Research Trend ◽  
Cmos Process ◽  
Clock Generator ◽  
Locking Range ◽  
Phase Interpolator ◽  
Chip Size ◽  
Calibration Free

Sampling-based PLLs have become a new research trend due to the possibility of removing the frequency divider (FDIV) from the feedback path, where the FDIV increases the contribution of in-band noise by the factor of dividing ratio square (N2). Between two possible sampling methods, sub-sampling and reference-sampling, the latter provides a relatively wide locking range, as the slower input reference signal is sampled with the faster VCO output signal. However, removal of FDIV makes the PLL not feasible to implement fractional-N operation based on varying divider ratios through random sequence generators, such as a Delta-Sigma-Modulator (DSM). To address the above design challenges, we propose a reference-sampling-based calibration-free fractional-N PLL (RSFPLL) with a phase-interpolator-linked sampling clock generator (PSCG). The proposed RSFPLL achieves fractional-N operations through phase-interpolator (PI)-based multi-phase generation instead of a typical frequency divider or digital-to-time converter (DTC). In addition, to alleviate the power burden arising from VCO-rated sampling, a flexible mask window generation method has been used that only passes a few sampling clocks near the point of interest. The prototype PLL system is designed with a 65 nm CMOS process with a chip size of 0.42 mm2. It achieves 322 fs rms jitter, −240.7 dB figure-of-merit (FoM), and −44.06 dBc fractional spurs with 8.17 mW power consumption.

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