2-channel 2-layer inner-stack memory-module design for LPDDR2/3 DRAM

Author(s):  
Jongjoo Lee ◽  
Joon Ki Paek ◽  
Joonhee Lee
Keyword(s):  
1973 ◽  
Vol 9 (3) ◽  
pp. 436-440 ◽  
Author(s):  
P. Michaelis ◽  
P. Bonyhard

2011 ◽  
Vol 26 (12) ◽  
pp. 1261-1265 ◽  
Author(s):  
Hui MA ◽  
Zhi-Yong LIU ◽  
Yu-Ming LU ◽  
Xiao-Yan JIN ◽  
Chuan-Bing CAI

2012 ◽  
Vol 220-223 ◽  
pp. 1472-1475
Author(s):  
Qiu Lin Tan ◽  
Xiang Dong Pei ◽  
Si Min Zhu ◽  
Ji Jun Xiong

On the basis of automatic test system of the status in domestic and foreign, by analysis of the various functions and performance of the integrated test system, a design of the integrated test system is proposed, FPGA as the core logic controller of the hardware circuit. The system of the hardware design include: digital signal source output modules, analog output module and PCM codec module. Design of hardware circuit are mainly described. In addition, a detailed analysis of some key technologies in the design process was given. Overall, its data exchange with host computer is through the PCI card, data link and bandwidth can be expanded in accordance with the actual needs. The entire system designed in the modular principle, which has a strong scalability.


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