Instruction Profiling Based Fetch Throttling for Wasted Dynamic Power Reduction

2019 31st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD) ◽

10.1109/sbac-pad.2019.00018 ◽

2019 ◽

Author(s):

Abdullah A. Owahid ◽

Eugene B. John

Keyword(s):

Power Reduction ◽

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3.37 μW/Ch modular scalable neural recording system with embedded lossless compression for dynamic power reduction

2017 Symposium on VLSI Circuits ◽

10.23919/vlsic.2017.8008468 ◽

2017 ◽

Author(s):

Sung-Yun Park ◽

Jihyun Cho ◽

Euisik Yoon

Keyword(s):

Lossless Compression ◽

Neural Recording ◽

Power Reduction ◽

Recording System ◽

Dynamic Power ◽

Neural Recording System

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Circuits Techniques for Dynamic Power Reduction

Computer Engineering Series - Low-Power Electronics Design ◽

10.1201/9781420039559.ch10 ◽

2004 ◽

pp. 10-1-10-21

Author(s):

Dimitrios Soudris

Keyword(s):

Power Reduction ◽

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Impact of scaling on the effectiveness of dynamic power reduction schemes

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.2002.1106798 ◽

2003 ◽

Author(s):

D. Duarte ◽

N. Vijaykrishnan ◽

M.J. Irwin ◽

H.-S. Kim ◽

G. McFarland

Keyword(s):

Power Reduction ◽

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Drive Strength and LVCMOS Based Dynamic Power Reduction of ALU on FPGA

Lecture Notes on Information Theory ◽

10.12720/lnit.1.1.60-63 ◽

2013 ◽

Vol 1 (1) ◽

pp. 60-63 ◽

Author(s):

Bishwajeet Pandey ◽

Mayank Kumar ◽

Nirmal Roberts ◽

Manisha Pattanaik

Keyword(s):

Power Reduction ◽

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Static and Dynamic Power Reduction by Architecture Selection

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/11847083_65 ◽

2006 ◽

pp. 659-668 ◽

Author(s):

Christian Piguet ◽

Christian Schuster ◽

Jean-Luc Nagel

Keyword(s):

Power Reduction ◽

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Dynamic Power Reduction Techniques for CMOS Logics Using 45 nm Technology

International Conference on Intelligent Computing and Smart Communication 2019 - Algorithms for Intelligent Systems ◽

10.1007/978-981-15-0633-8_112 ◽

2019 ◽

pp. 1117-1126

Author(s):

Rajesh Yadav ◽

Reetu ◽

Rekha Yadav

Keyword(s):

Power Reduction ◽

Dynamic Power ◽

Reduction Techniques

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A Dynamic Power Reduction Methodology based on Reducing Output Transition Rate

2019 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM) ◽

10.1109/pacrim47961.2019.8985099 ◽

2019 ◽

Author(s):

Moaz Mostafa ◽

Ahmed M. Zaki ◽

M. Watheq El-Kharashi ◽

Mohamed Dessouky

Keyword(s):

Transition Rate ◽

Power Reduction ◽

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Dynamic power reduction through clock gating technique for low power memory applications

2015 IEEE International Conference on Electrical, Computer and Communication Technologies (ICECCT) ◽

10.1109/icecct.2015.7226204 ◽

2015 ◽

Author(s):

G. S. R. Srivatsava ◽

Pooran Singh ◽

Siddharth Gaggar ◽

Santosh Kumar Vishvakarma

Keyword(s):

Low Power ◽

Power Reduction ◽

Clock Gating ◽

Dynamic Power ◽

Memory Applications

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Design of low power and high performance router using dynamic power reduction technique

2012 International Conference on Devices, Circuits and Systems (ICDCS) ◽

10.1109/icdcsyst.2012.6188672 ◽

2012 ◽

Author(s):

L. N. Thalluri ◽

S. B. Sukhavasi ◽

S. B. Sukhavasi ◽

K. K. Tatineni ◽

S. R. Sastry Kalavakolanu

Keyword(s):

Low Power ◽

High Performance ◽

Power Reduction ◽

Reduction Technique ◽

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Dynamic Power Reduction of Digital Circuits by ClockGating

International Journal of Engineering Research and Applications ◽

10.9790/9622-0704050911 ◽

2017 ◽

Vol 07 (04) ◽

pp. 09-11

Author(s):

Varsha Dewre ◽

Rakesh Mandliya

Keyword(s):

Digital Circuits ◽

Power Reduction ◽

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