Performance Analysis and Optimization of User Space versus Kernel Space Network Application

Author(s):  
Koh Minghao ◽  
Khong Yun Chyang ◽  
Ettikan Kandasamy Karuppiah
Author(s):  
Paul Emmerich ◽  
Maximilian Pudelko ◽  
Simon Bauer ◽  
Stefan Huber ◽  
Thomas Zwickl ◽  
...  
Keyword(s):  

Micromachines ◽  
2020 ◽  
Vol 11 (12) ◽  
pp. 1075
Author(s):  
Tao Cai ◽  
Qingjian He ◽  
Dejiao Niu ◽  
Fuli Chen ◽  
Jie Wang ◽  
...  

The non-volatile memory (NVM) device is a useful way to solve the memory wall in computers. However, the current I/O software stack in operating systems becomes a performance bottleneck for applications based on NVM devices, especially for key–value stores. We analyzed the characteristics of key–value stores and NVM devices and designed a new embedded key–value store for an NVM device simulator named PMEKV. The embedded processor in NVM devices was used to manage key–value pairs to reduce the data transfer between NVM devices and key–value applications. Meanwhile, it also cut down the data copy between the user space and the kernel space in the operating system to alleviate the I/O software stacks on the efficiency of key–value stores. The architecture, data layout, management strategy, new interface and log strategy of PMEKV are given. Finally, a prototype of PMEKV was implemented based on PMEM. We used YCSB to test and compare it with Redis, MongDB, and Memcache. Meanwhile, the Redis for PMEM named PMEM-Redis and PMEM-KV were also used to test and compared with PMEKV. The results show that PMEKV had the advantage of throughput and adaptability compared with the current key–value stores.


Author(s):  
Paul Emmerich ◽  
Maximilian Pudelko ◽  
Simon Bauer ◽  
Georg Carle
Keyword(s):  

Author(s):  
Dario Bruneo ◽  
Salvatore Distefano ◽  
Kostya Esmukov ◽  
Francesco Longo ◽  
Giovanni Merlino ◽  
...  

2003 ◽  
Vol 13 (02) ◽  
pp. 149-167 ◽  
Author(s):  
JEAN-PATRICK GELAS ◽  
SAAD EL HADRI ◽  
LAURENT LEFÈVRE

Achieving high performance in active networks is one of the most challenging task. In this paper, we propose an architecture for the design of next generation gigabit active routers . This original architecture allows service deployment of 4 levels: inside network cards, in kernel space, in user space and on distributed computing resources. We deploy and validate this architecture within the Tamanoir execution environment. First experiments on gigabit network platforms are described.


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