Compact modeling for application-specific high-sigma worst case

Packet classification is a ubiquitous and key building block for many critical network devices. However, it remains as one of the main bottlenecks faced when designing fast network devices. In this paper, we propose a novel Group Based Search packet classification Algorithm (GBSA) that is scalable, fast, and efficient. GBSA consumes an average of 0.4 megabytes of memory for a 10 k rule set. The worst-case classification time per packet is 2 microseconds, and the preprocessing speed is 3 M rules/second based on an Xeon processor operating at 3.4 GHz. When compared with other state-of-the-art classification techniques, the results showed that GBSA outperforms the competition with respect to speed, memory usage, and processing time. Moreover, GBSA is amenable to implementation in hardware. Three different hardware implementations are also presented in this paper including an Application Specific Instruction Set Processor (ASIP) implementation and two pure Register-Transfer Level (RTL) implementations based on Impulse-C and Handel-C flows, respectively. Speedups achieved with these hardware accelerators ranged from 9x to 18x compared with a pure software implementation running on an Xeon processor.

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Application-specific worst case corners using response surfaces and statistical models

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2005.852037 ◽

2005 ◽

Vol 24 (9) ◽

pp. 1372-1380 ◽

Cited By ~ 40

Author(s):

M. Sengupta ◽

S. Saxena ◽

L. Daldoss ◽

G. Kramer ◽

S. Minehane ◽

...

Keyword(s):

Statistical Models ◽

Response Surfaces ◽

Worst Case ◽

Application Specific

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Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures

10.32920/ryerson.14649366 ◽

2021 ◽

Author(s):

Anita Tino

Keyword(s):

Tabu Search ◽

Network On Chip ◽

Computational Time ◽

Multiprocessor System ◽

Case Scenario ◽

Worst Case ◽

Multi Objective ◽

And Performance ◽

On Chip ◽

Application Specific

Network-on-Chip (NoC) communication interconnects have emerged as a solution to complex heterogeneous core systems such as those found in Multiprocessor System-on-Chip architectures. Many previous works have used the objectives of power or performance during topology synthesis for regular or application specific based NoC design. However, given the crucial requirements and demands of future on-chip applications, it is imperative that designs consider both power and performance aspects, in addition to other important system constraints. Therefore, in order to address such issues, this thesis work presents a multi-objective Tabu search based topology synthesis technique for designing power and performance efficient Network-on-Chip architectures. The methodology incorporates an analytical and simulation approach in order to compromise between computational time and effort within the algorithm. Furthermore, this work also presents a novel approach for a power and performance tradeoff during contention and deadlock removal within synthesis. The proposed method was tested using seven different multimedia and network benchmark application, where results displayed an increase in performance and decrease in power dissipation in comparison to other previous application specific and regular mesh designs. The analysis method was successful during topology generation, yielding an overall accuracy rate deviation of 19.8% within the worst case scenario.

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Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures

10.32920/ryerson.14649366.v1 ◽

2021 ◽

Author(s):

Anita Tino

Keyword(s):

Tabu Search ◽

Network On Chip ◽

Computational Time ◽

Multiprocessor System ◽

Case Scenario ◽

Worst Case ◽

Multi Objective ◽

And Performance ◽

On Chip ◽

Application Specific

Network-on-Chip (NoC) communication interconnects have emerged as a solution to complex heterogeneous core systems such as those found in Multiprocessor System-on-Chip architectures. Many previous works have used the objectives of power or performance during topology synthesis for regular or application specific based NoC design. However, given the crucial requirements and demands of future on-chip applications, it is imperative that designs consider both power and performance aspects, in addition to other important system constraints. Therefore, in order to address such issues, this thesis work presents a multi-objective Tabu search based topology synthesis technique for designing power and performance efficient Network-on-Chip architectures. The methodology incorporates an analytical and simulation approach in order to compromise between computational time and effort within the algorithm. Furthermore, this work also presents a novel approach for a power and performance tradeoff during contention and deadlock removal within synthesis. The proposed method was tested using seven different multimedia and network benchmark application, where results displayed an increase in performance and decrease in power dissipation in comparison to other previous application specific and regular mesh designs. The analysis method was successful during topology generation, yielding an overall accuracy rate deviation of 19.8% within the worst case scenario.

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Mosaic Mapping: A Means of Tiling Images to Shorten Acquisition Speed for Lower - Magnification SEM Images and Wavelength Dispersive Spectrometers (WDS) X-Ray Maps

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100164659 ◽

1996 ◽

Vol 54 ◽

pp. 438-439

Author(s):

J.D. Geller ◽

C.R. Herrington

Keyword(s):

Limiting Factors ◽

X Rays ◽

Angular Range ◽

Acceptance Angle ◽

Sem Images ◽

Worst Case ◽

X Ray ◽

Focusing Distance ◽

Layered Crystals ◽

Working Distance

The minimum magnification for which an image can be acquired is determined by the design and implementation of the electron optical column and the scanning and display electronics. It is also a function of the working distance and, possibly, the accelerating voltage. For secondary and backscattered electron images there are usually no other limiting factors. However, for x-ray maps there are further considerations. The energy-dispersive x-ray spectrometers (EDS) have a much larger solid angle of detection that for WDS. They also do not suffer from Bragg’s Law focusing effects which limit the angular range and focusing distance from the diffracting crystal. In practical terms EDS maps can be acquired at the lowest magnification of the SEM, assuming the collimator does not cutoff the x-ray signal. For WDS the focusing properties of the crystal limits the angular range of acceptance of the incident x-radiation. The range is dependent upon the 2d spacing of the crystal, with the acceptance angle increasing with 2d spacing. The natural line width of the x-ray also plays a role. For the metal layered crystals used to diffract soft x-rays, such as Be - O, the minimum magnification is approximately 100X. In the worst case, for the LEF crystal which diffracts Ti - Zn, ˜1000X is the minimum.

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