FPGA implementation of layered low density parity check error correction codes

2017 ◽  
Author(s):  
Abdulsamet Caglan ◽  
Ersen Balcisoy ◽  
Emre Kirkaya ◽  
Gurbannazar Charyyev ◽  
Adem Cicek ◽  
...  
Keyword(s):  
Error Correction ◽  
Fpga Implementation ◽  
Error Correction Codes ◽  
Low Density ◽  
Parity Check ◽  
Low Density Parity Check ◽  
Check Error

Spatially coupled low-density parity-check error correction for holographic data storage

2017 ◽  
Vol 56 (9S) ◽  
pp. 09NA03
Author(s):  
Norihiko Ishii ◽  
Yutaro Katano ◽  
Tetsuhiko Muroi ◽  
Nobuhiro Kinoshita
Keyword(s):  
Error Correction ◽  
Data Storage ◽  
Holographic Data Storage ◽  
Low Density ◽  
Parity Check ◽  
Low Density Parity Check ◽  
Check Error

GRAPHICAL QUANTUM LOW-DENSITY PARITY-CHECK CODES

2012 ◽  
Vol 26 (20) ◽  
pp. 1250118
Author(s):  
YUAN LI ◽  
MANTAO XU ◽  
YINKUO MENG ◽  
YING GUO
Keyword(s):  
Error Correction ◽  
Fast Algorithm ◽  
Ldpc Codes ◽  
Quantum Codes ◽  
Error Correction Codes ◽  
Low Density ◽  
Parity Check ◽  
Graphical Approach ◽  
Low Density Parity Check ◽  
Parity Check Codes

Graphical approach provides a direct way to construct error correction codes. Motivated by its good properties, associating low-density parity-check (LDPC) codes, in this paper we present families of graphical quantum LDPC codes which contain no girth of four. Because of the fast algorithm of constructing for graphical codes, the proposed quantum codes have lower encoding complexity.

Method of Combining Cryptography and LDPC Coding for Enhanced Privacy

2021 ◽  
Vol 13 (4) ◽  
pp. 51-70
Author(s):  
Bradley Comar
Keyword(s):  
Error Correction ◽  
Pseudorandom Number ◽  
Low Density ◽  
Parity Check ◽  
Pseudorandom Number Generators ◽  
Low Density Parity Check

This paper describes a method of combining cryptographic encoding and low density parity check (LDPC) encoding for the purpose of enhancing privacy. This method uses pseudorandom number generators (PRNGs) to create parity check matrices that are constantly updated. The generated cyphertext is at least as private as a standard additive (XORing) cryptosystem, and also has error correcting capability. The eavesdropper, Eve, has the expanded burden of having to perform cryptanalysis and error correction simultaneously.

Nonbinary Low-Density Parity Check Decoding Algorithm Research-Based Majority Logic Decoding

2020 ◽  
Vol 34 (12) ◽  
pp. 2058016
Author(s):  
Zhong-xun Wang ◽  
Yang Xi ◽  
Zhan-kai Bao
Keyword(s):  
Error Correction ◽  
Iterative Decoding ◽  
Hamming Distance ◽  
Low Density ◽  
Parity Check ◽  
Soft Decision ◽  
Decoding Algorithm ◽  
Majority Logic ◽  
Low Density Parity Check ◽  
Majority Logic Decoding

In the nonbinary low-density parity check (NB-LDPC) codes decoding algorithms, the iterative hard reliability based on majority logic decoding (IHRB-MLGD) algorithm has poor error correction performance. The essential reason is that the hard information is used in the initialization and iterative processes. For the problem of partial loss of information, when the reliability is assigned during initialization, the error correction performance is improved by modifying the assignment of reliability at initialization. The initialization process is determined by the probability of occurrence of the number of erroneous bits in the symbol and the Hamming distance. In addition, the IHRB-MLGD decoding algorithm uses the hard decision in the iterative decoding process. The improved algorithm adds soft decision information in the iterative process, which improves the error correction performance while only slightly increasing the decoding complexity, and improves the reliability accumulation process which makes the algorithm more stable. The simulation results indicate that the proposed algorithm has a better decoding performance than IHRB algorithm.

FPGA Implementation of a Novel Multi-Rate QC-LDPC Encoder for DTMB Standard

2013 ◽  
Vol 397-400 ◽  
pp. 2024-2027
Author(s):  
Fei Wang ◽  
Peng Zhang ◽  
Chang Yin Liu
Keyword(s):  
Power Consumption ◽  
Ldpc Codes ◽  
Fpga Implementation ◽  
Type I ◽  
Low Density ◽  
Parity Check ◽  
Encoding Scheme ◽  
Low Density Parity Check ◽  
Memory Resource ◽  
Simulation Results

A serial-input serial-output encoder based on pipelined type I rotate-left-accumulator (RLA) circuit is presented for multi-rate Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes of Digital Terrestrial Multimedia Broadcasting (DTMB) standard. This encoding scheme can reduce the power consumption and save memory resource. FPGA implementation and simulation results show that the design meets the requirement of DTMB standard and simplifies the structure of the memory.

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