A unified HW/SW system-level simulation framework for next generation wireless system

2017 ◽  
Author(s):  
N. Sutisna ◽  
L. Lanante ◽  
Y. Nagao ◽  
M. Kurosaki ◽  
H. Ochi
Keyword(s):  
System Level ◽  
Next Generation ◽  
Simulation Framework ◽  
Wireless System ◽  
System Level Simulation

scholarly journals Downlink Power Allocation Strategy for Next-Generation Underwater Acoustic Communications Networks

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1297 ◽  
Author(s):  
Ahmad ◽  
Chang
Keyword(s):  
Power Allocation ◽  
Base Station ◽  
System Level ◽  
Underwater Acoustic Communications ◽  
Frequency Division ◽  
Next Generation ◽  
Acoustic Communications ◽  
Underwater Acoustic ◽  
Communications Networks ◽  
System Level Simulation

The increasing interest in next-generation underwater acoustic communications networks is due to vast investigation of oceans for oceanography, commercial operations in maritime areas, military surveillance, and more. A surface buoy or underwater base station controller (UBSC) communicates with either transceivers or underwater base stations (UBSs) via acoustic links. Transceivers further communicate with underwater sensor nodes using acoustic links. In this paper, we employ a downlink (DL) power allocation (PA) strategy using an orthogonal frequency-division multiple access (OFDMA) technique for underwater acoustic communications (UAC) networks. First, we present an approach to power offsets using three kinds of pilot spacing and apply the power boosting (PB) concept on orthogonal frequency-division multiplexing (OFDM) symbols for the UAC network. Secondly, we draw the block error rate (BLER) curves from link-level simulation (LLS) and analyze the signal-to-noise ratio (SNR) for both PA and non-PA strategies. Lastly, we adopt the best PB for system-level simulation (SLS) and compare the throughput and outage performance for PA and non-PA strategies. Hence, the simulation results confirm the effectiveness of the DL PA strategy for UAC networks.

scholarly journals Gem5-X: A Gem5-Based System Level Simulation Framework to Optimize Many-Core Platforms

2019 ◽  
Author(s):  
Yasir Mahmood Qureshi ◽  
William Andrew Simon ◽  
Marina Zapater ◽  
David Atienza ◽  
Katzalin Olcoz
Keyword(s):  
System Level ◽  
Simulation Framework ◽  
System Level Simulation ◽  
Many Core

scholarly journals Real-Time Vehicular Wireless System-Level Simulation

IEEE Access ◽  
2021 ◽  
Vol 9 ◽  
pp. 23202-23217
Author(s):  
Anja Dakic ◽  
Markus Hofer ◽  
Benjamin Rainer ◽  
Stefan Zelenbaba ◽  
Laura Bernado ◽  
...  
Keyword(s):  
Real Time ◽  
System Level ◽  
Wireless System ◽  
System Level Simulation

Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level Simulation

2022 ◽  
Vol 21 (1) ◽  
pp. 1-25
Author(s):  
Kazi Asifuzzaman ◽  
Rommel Sánchez Verdejo ◽  
Petar Radojković
Keyword(s):  
Academic Research ◽  
Random Access ◽  
Power Estimation ◽  
Spin Transfer Torque ◽  
Main Memory ◽  
System Level ◽  
Next Generation ◽  
Reliable System ◽  
Novel Technology ◽  
System Level Simulation

It is questionable whether DRAM will continue to scale and will meet the needs of next-generation systems. Therefore, significant effort is invested in research and development of novel memory technologies. One of the candidates for next-generation memory is Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM). STT-MRAM is an emerging non-volatile memory with a lot of potential that could be exploited for various requirements of different computing systems. Being a novel technology, STT-MRAM devices are already approaching DRAM in terms of capacity, frequency, and device size. Although STT-MRAM technology got significant attention of various major memory manufacturers, academic research of STT-MRAM main memory remains marginal. This is mainly due to the unavailability of publicly available detailed timing and current parameters of this novel technology, which are required to perform a reliable main memory simulation on performance and power estimation. This study demonstrates an approach to perform a cycle accurate simulation of STT-MRAM main memory, being the first to release detailed timing and current parameters of this technology from academia—essentially enabling researchers to conduct reliable system-level simulation of STT-MRAM using widely accepted existing simulation infrastructure. The results show a fairly narrow overall performance deviation in response to significant variations in key timing parameters, and the power consumption experiments identify the key power component that is mostly affected with STT-MRAM.

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