Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level Simulation

2022 ◽  
Vol 21 (1) ◽  
pp. 1-25
Author(s):  
Kazi Asifuzzaman ◽  
Rommel Sánchez Verdejo ◽  
Petar Radojković
Keyword(s):  
Academic Research ◽  
Random Access ◽  
Power Estimation ◽  
Spin Transfer Torque ◽  
Main Memory ◽  
System Level ◽  
Next Generation ◽  
Reliable System ◽  
Novel Technology ◽  
System Level Simulation

It is questionable whether DRAM will continue to scale and will meet the needs of next-generation systems. Therefore, significant effort is invested in research and development of novel memory technologies. One of the candidates for next-generation memory is Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM). STT-MRAM is an emerging non-volatile memory with a lot of potential that could be exploited for various requirements of different computing systems. Being a novel technology, STT-MRAM devices are already approaching DRAM in terms of capacity, frequency, and device size. Although STT-MRAM technology got significant attention of various major memory manufacturers, academic research of STT-MRAM main memory remains marginal. This is mainly due to the unavailability of publicly available detailed timing and current parameters of this novel technology, which are required to perform a reliable main memory simulation on performance and power estimation. This study demonstrates an approach to perform a cycle accurate simulation of STT-MRAM main memory, being the first to release detailed timing and current parameters of this technology from academia—essentially enabling researchers to conduct reliable system-level simulation of STT-MRAM using widely accepted existing simulation infrastructure. The results show a fairly narrow overall performance deviation in response to significant variations in key timing parameters, and the power consumption experiments identify the key power component that is mostly affected with STT-MRAM.

scholarly journals Downlink Power Allocation Strategy for Next-Generation Underwater Acoustic Communications Networks

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1297 ◽  
Author(s):  
Ahmad ◽  
Chang
Keyword(s):  
Power Allocation ◽  
Base Station ◽  
System Level ◽  
Underwater Acoustic Communications ◽  
Frequency Division ◽  
Next Generation ◽  
Acoustic Communications ◽  
Underwater Acoustic ◽  
Communications Networks ◽  
System Level Simulation

The increasing interest in next-generation underwater acoustic communications networks is due to vast investigation of oceans for oceanography, commercial operations in maritime areas, military surveillance, and more. A surface buoy or underwater base station controller (UBSC) communicates with either transceivers or underwater base stations (UBSs) via acoustic links. Transceivers further communicate with underwater sensor nodes using acoustic links. In this paper, we employ a downlink (DL) power allocation (PA) strategy using an orthogonal frequency-division multiple access (OFDMA) technique for underwater acoustic communications (UAC) networks. First, we present an approach to power offsets using three kinds of pilot spacing and apply the power boosting (PB) concept on orthogonal frequency-division multiplexing (OFDM) symbols for the UAC network. Secondly, we draw the block error rate (BLER) curves from link-level simulation (LLS) and analyze the signal-to-noise ratio (SNR) for both PA and non-PA strategies. Lastly, we adopt the best PB for system-level simulation (SLS) and compare the throughput and outage performance for PA and non-PA strategies. Hence, the simulation results confirm the effectiveness of the DL PA strategy for UAC networks.

Accurate power estimation of hardware co-processors using system level simulation

2009 ◽  
Author(s):  
Sumit Ahuja ◽  
Deepak A. Mathaikutty ◽  
Avinash Lakshminarayana ◽  
Sandeep Shukla
Keyword(s):  
Power Estimation ◽  
System Level ◽  
System Level Simulation

scholarly journals Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches

Electronics ◽  
2022 ◽  
Vol 11 (2) ◽  
pp. 240
Author(s):  
Beomjun Kim ◽  
Yongtae Kim ◽  
Prashant Nair ◽  
Seokin Hong
Keyword(s):  
Random Access ◽  
Spin Transfer Torque ◽  
Main Memory ◽  
Spin Transfer ◽  
Access Memory ◽  
Low Leakage ◽  
Block Placement ◽  
On Chip ◽  
Hybrid Caches ◽  
Cache Block

STT-RAM (Spin-Transfer Torque Random Access Memory) appears to be a viable alternative to SRAM-based on-chip caches. Due to its high density and low leakage power, STT-RAM can be used to build massive capacity last-level caches (LLC). Unfortunately, STT-RAM has a much longer write latency and a much greater write energy than SRAM. Researchers developed hybrid caches made up of SRAM and STT-RAM regions to cope with these challenges. In order to store as many write-intensive blocks in the SRAM region as possible in hybrid caches, an intelligent block placement policy is essential. This paper proposes an adaptive block placement framework for hybrid caches that incorporates metadata embedding (ADAM). When a cache block is evicted from the LLC, ADAM embeds metadata (i.e., write intensity) into the block. Metadata embedded in the cache block are then extracted and used to determine the block’s write intensity when it is fetched from main memory. Our research demonstrates that ADAM can enhance performance by 26% (on average) when compared to a baseline block placement scheme.

scholarly journals Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories

2021 ◽  
Vol 11 (4) ◽  
pp. 36
Author(s):  
Mohammad Nasim Imtiaz Khan ◽  
Swaroop Ghosh
Keyword(s):  
Data Privacy ◽  
New Technologies ◽  
Spin Transfer Torque ◽  
Main Memory ◽  
Security And Privacy ◽  
System Level ◽  
System Throughput ◽  
Privacy And Security ◽  
Von Neumann ◽  
Privacy Issues

Several promising non-volatile memories (NVMs) such as magnetic RAM (MRAM), spin-transfer torque RAM (STTRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), and phase-change memory (PCM) are being investigated to keep the static leakage within a tolerable limit. These new technologies offer high density and consume zero leakage power and can bridge the gap between processor and memory. The desirable properties of emerging NVMs make them suitable candidates for several applications including replacement of conventional memories. However, their unique characteristics introduce new data privacy and security issues. Some of them are already available in the market as discrete chips or a part of full system implementation. They are considered to become ubiquitous in future computing devices. Therefore, it is important to ensure their security/privacy issues. Note that these NVMs can be considered for cache, main memory, or storage application. They are also suitable to implement in-memory computation which increases system throughput and eliminates von Neumann bottleneck. Compute-capable NVMs impose new security and privacy challenges that are fundamentally different than their storage counterpart. This work identifies NVM vulnerabilities and attack vectors originating from the device level all the way to circuits and systems, considering both storage and compute applications. We also summarize the circuit/system-level countermeasures to make the NVMs robust against security and privacy issues.

Materials, Devices and Spin Transfer Torque in Antiferromagnetic Spintronics: A Concise Review

SPIN ◽  
2017 ◽  
Vol 07 (03) ◽  
pp. 1740014 ◽  
Author(s):  
Cormac Ó Coileáin ◽  
Han Chun Wu
Keyword(s):  
Magnetic Fields ◽  
Spin Transfer Torque ◽  
Spin Transfer ◽  
Tetragonal Structure ◽  
Next Generation ◽  
Tunnel Magnetoresistance ◽  
Spintronic Devices ◽  
Concise Review ◽  
Plane Anisotropy ◽  
Magnetic States

From historical obscurity, antiferromagnets are recently enjoying revived interest, as antiferromagnetic (AFM) materials may allow the continued reduction in size of spintronic devices. They have the benefit of being insensitive to parasitic external magnetic fields, while displaying high read/write speeds, and thus poised to become an integral part of the next generation of logical devices and memory. They are currently employed to preserve the magnetoresistive qualities of some ferromagnetic based giant or tunnel magnetoresistance systems. However, the question remains how the magnetic states of an antiferromagnet can be efficiently manipulated and detected. Here, we reflect on AFM materials for their use in spintronics, in particular, newly recognized antiferromagnet Mn2Au with its in-plane anisotropy and tetragonal structure and high Néel temperature. These attributes make it one of the most promising candidates for AFM spintronics thus far with the possibility of architectures freed from the need for ferromagnetic (FM) elements. Here, we discuss its potential for use in ferromagnet-free spintronic devices.

scholarly journals System Level Simulation of Microgrid Power Electronic Systems

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 644
Author(s):  
Michal Frivaldsky ◽  
Jan Morgos ◽  
Michal Prazenica ◽  
Kristian Takacs
Keyword(s):  
Smart Grid ◽  
Simulation Model ◽  
Real Time ◽  
Power Converter ◽  
System Level ◽  
Time Behavior ◽  
Operational Parameters ◽  
System Level Simulation ◽  
Time Operation ◽  
The Impact

In this paper, we describe a procedure for designing an accurate simulation model using a price-wised linear approach referred to as the power semiconductor converters of a DC microgrid concept. Initially, the selection of topologies of individual power stage blocs are identified. Due to the requirements for verifying the accuracy of the simulation model, physical samples of power converters are realized with a power ratio of 1:10. The focus was on optimization of operational parameters such as real-time behavior (variable waveforms within a time domain), efficiency, and the voltage/current ripples. The approach was compared to real-time operation and efficiency performance was evaluated showing the accuracy and suitability of the presented approach. The results show the potential for developing complex smart grid simulation models, with a high level of accuracy, and thus the possibility to investigate various operational scenarios and the impact of power converter characteristics on the performance of a smart gird. Two possible operational scenarios of the proposed smart grid concept are evaluated and demonstrate that an accurate hardware-in-the-loop (HIL) system can be designed.

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