scholarly journals Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits

Author(s):  
P. Rosinger ◽  
B.M. Al-Hashimi ◽  
K. Chakrabarty
2020 ◽  
pp. 1-13
Author(s):  
Gokul Chandrasekaran ◽  
P.R. Karthikeyan ◽  
Neelam Sanjeev Kumar ◽  
Vanchinathan Kumarasamy

Test scheduling of System-on-Chip (SoC) is a major problem solved by various optimization techniques to minimize the cost and testing time. In this paper, we propose the application of Dragonfly and Ant Lion Optimization algorithms to minimize the test cost and test time of SoC. The swarm behavior of dragonfly and hunting behavior of Ant Lion optimization methods are used to optimize the scheduling time in the benchmark circuits. The proposed algorithms are tested on p22810 and d695 ITC’02 SoC benchmark circuits. The results of the proposed algorithms are compared with other algorithms like Ant Colony Optimization, Modified Ant Colony Optimization, Artificial Bee Colony, Modified Artificial Bee Colony, Firefly, Modified Firefly, and BAT algorithms to highlight the benefits of test time minimization. It is observed that the test time obtained for Dragonfly and Ant Lion optimization algorithms is 0.013188 Sec for D695, 0.013515 Sec for P22810, and 0.013432 Sec for D695, 0.013711 Sec for P22810 respectively with TAM Width of 64, which is less as compared to the other well-known optimization algorithms.


Author(s):  
Ran Wang ◽  
Guoliang Li ◽  
Rui Li ◽  
Jun Qian ◽  
Krishnendu Chakrabarty

2018 ◽  
Vol 24 (1) ◽  
pp. 1-20 ◽  
Author(s):  
Fred Kish ◽  
Vikrant Lal ◽  
Peter Evans ◽  
Scott W. Corzine ◽  
Mehrdad Ziari ◽  
...  

2019 ◽  
Vol 32 (9) ◽  
pp. 5303-5312 ◽  
Author(s):  
Gokul Chandrasekaran ◽  
Sakthivel Periyasamy ◽  
Karthikeyan Panjappagounder Rajamanickam

2019 ◽  
Vol 1 (9) ◽  
Author(s):  
Gokul Chandrasekaran ◽  
Sakthivel Periyasamy ◽  
P. R. Karthikeyan

Sign in / Sign up

Export Citation Format

Share Document