The run length based coding schemes have been very effective for
the test data compression in case of current generation SoCs with
a large number of IP cores. The first part of paper presents a
survey of the run length based codes. The data compression of any
partially specified test data depends upon how the unspecified
bits are filled with 1s and 0s. In the second part of the paper,
the five different approaches for “don't care” bit
filling based on nature of runs are proposed to predict the
maximum compression based on entropy. Here the various run length
based schemes are compared with maximum data compression limit
based on entropy bounds. The actual compressions claimed by the
authors are also compared. For various ISCAS circuits, it has been
shown that when the X filling is done considering runs of zeros
followed by one as well as runs of ones followed by zero (i.e.,
Extended FDR), it provides the maximum data compression. In third
part, it has been shown that the average test power and peak power
is minimum when the don't care bits are filled to make the
long runs of 0s as well as 1s.
Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression