CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management

Author(s):  
Da-Wei Chang ◽  
Ing-Chao Lin ◽  
Yu-Shiang Chien ◽  
Chin-Lun Lin ◽  
Alvin W.-Y Su ◽  
...  
2013 ◽  
Vol 748 ◽  
pp. 932-935
Author(s):  
Ze Yu Zuo ◽  
Wei Hu ◽  
Rui Xin Hu ◽  
Heng Xiong ◽  
Wen Bin Du ◽  
...  

Mobile devices have been popular in recent years and the proliferation of mobile devices inspires the interest in mobile multimedia applications. However, memory is always the bottleneck in the traditional memory hierarchy. Scratchpad memory (SPM) is a promising on-chip SRAM to solve such problem. It has faster access time and less power-consumption compared to cache and off-chip memory. In this paper, we propose the efficient scratchpad memory management approach for mobile multimedia applications. SPM is partitioned for the assignment of the slices of the applications based on the profiling and the recorded history. Through the use of SPM, the memory footprint of mobile multimedia applications will be reduced for better performance and less power-consumption. The experimental results show that our approach is able to significantly reduce the power consumption and improve the performance of mobile multimedia applications.


Author(s):  
Kavita Tabbassum ◽  
Shah Nawaz Talpur ◽  
Sanam Narejo ◽  
Noor-u-Zaman Leghari

Consuming the conventional approaches, processors are incapable to achieve effective energy reduction. In upcoming processors on-chip memory system will be the major restriction. On-chip memories are managed by the software SMCs (Software Managed Chips), and are work with caches (on-chip), where inside a block of caches software can explicitly read as well as write specific or complete memory references, or work separately just like scratchpad memory. In embedded systems Scratch memory is generally used as an addition to caches or as a substitute of cache, but due to their comprehensive ease of programmability cache containing architectures are still to be chosen in numerous applications. In contrast to conventional caches in embedded schemes because of their better energy and silicon range effectiveness SPM (Scratch-Pad Memories) are being progressively used. Power consumption of ported applications can significantly be lower as well as portability of scratchpad architectures will be advanced with the language agnostic software management method which is suggested in this manuscript. To enhance the memory configuration and optimization on relevant architectures based on SPM, the variety of current methods are reviewed for finding the chances of optimizations and usage of new methods as well as their applicability to numerous schemes of memory management are also discussed in this paper.


Author(s):  
D. Archer ◽  
D. Deverell ◽  
F. Fox ◽  
P. Gronowski ◽  
A. Jain ◽  
...  

Author(s):  
Xiaohan Tao ◽  
Jianmin Pang ◽  
Jinlong Xu ◽  
Yu Zhu

AbstractThe heterogeneous many-core architecture plays an important role in the fields of high-performance computing and scientific computing. It uses accelerator cores with on-chip memories to improve performance and reduce energy consumption. Scratchpad memory (SPM) is a kind of fast on-chip memory with lower energy consumption compared with a hardware cache. However, data transfer between SPM and off-chip memory can be managed only by a programmer or compiler. In this paper, we propose a compiler-directed multithreaded SPM data transfer model (MSDTM) to optimize the process of data transfer in a heterogeneous many-core architecture. We use compile-time analysis to classify data accesses, check dependences and determine the allocation of data transfer operations. We further present the data transfer performance model to derive the optimal granularity of data transfer and select the most profitable data transfer strategy. We implement the proposed MSDTM on the GCC complier and evaluate it on Sunway TaihuLight with selected test cases from benchmarks and scientific computing applications. The experimental result shows that the proposed MSDTM improves the application execution time by 5.49$$\times$$ × and achieves an energy saving of 5.16$$\times$$ × on average.


2020 ◽  
Vol 14 (3) ◽  
pp. 241-254
Author(s):  
Chen Luo ◽  
Michael J. Carey

Log-Structured Merge-trees (LSM-trees) have been widely used in modern NoSQL systems. Due to their out-of-place update design, LSM-trees have introduced memory walls among the memory components of multiple LSM-trees and between the write memory and the buffer cache. Optimal memory allocation among these regions is non-trivial because it is highly workload-dependent. Existing LSM-tree implementations instead adopt static memory allocation schemes due to their simplicity and robustness, sacrificing performance. In this paper, we attempt to break down these memory walls in LSM-based storage systems. We first present a memory management architecture that enables adaptive memory management. We then present a partitioned memory component structure with new flush policies to better exploit the write memory to minimize the write cost. To break down the memory wall between the write memory and the buffer cache, we further introduce a memory tuner that tunes the memory allocation between these two regions. We have conducted extensive experiments in the context of Apache AsterixDB using the YCSB and TPC-C benchmarks and we present the results here.


2011 ◽  
Vol 3 (2) ◽  
pp. 66-69 ◽  
Author(s):  
Iraklis Anagnostopoulos ◽  
Sotirios Xydis ◽  
Alexandros Bartzas ◽  
Zhonghai Lu ◽  
Dimitrios Soudris ◽  
...  

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