Low Complexity X-EMS Algorithms for Nonbinary LDPC Codes

2012 ◽  
Vol 60 (1) ◽  
pp. 9-13 ◽  
Author(s):  
Xiao Ma ◽  
Kai Zhang ◽  
Haiqiang Chen ◽  
Baoming Bai
2021 ◽  
Vol 2021 ◽  
pp. 1-16
Author(s):  
Wentao Fu ◽  
Xilun Luo ◽  
Yuanfa Ji ◽  
Xiyan Sun

For the conventional extended min-sum (EMS) algorithm, all check nodes update their check-to-variable (C2V) messages in every iteration. Selected scheduling, which reduces the number of check nodes for message updating in one iteration, can effectively reduce the complexity of the decoding algorithm, but it also lead to some performance degradation. With the introduction of a metric based on node stability, we propose stability-based node-subset scheduling (SNS) for the EMS algorithm, which can improve the performance of node-subset scheduling (NS). Second, to further improve the decoding performance of SNS while maintaining low complexity, we propose the SNS-EMS algorithm with a subset-reset mechanism (RSNS-EMS) based on the abnormal stability found in the processing node subset, which will cause the estimated codeword to fail to converge. The RSNS-EMS algorithm enhances performance through a sliding window detection and reset mechanism, and it resets the elements in the processing node subset to force all check nodes to update new messages when abnormal stability is detected. The simulation results show that the proposed algorithm can reduce complexity by approximately 25% with negligible performance degradation.


2010 ◽  
Vol 14 (11) ◽  
pp. 1062-1064 ◽  
Author(s):  
Dayuan Zhao ◽  
Xiao Ma ◽  
Chao Chen ◽  
Baoming Bai

Symmetry ◽  
2021 ◽  
Vol 13 (4) ◽  
pp. 700
Author(s):  
Yufei Zhu ◽  
Zuocheng Xing ◽  
Zerun Li ◽  
Yang Zhang ◽  
Yifan Hu

This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible with the 5th generation (5G) new radio (NR). Basing on the algorithm, we propose a high area-efficient parallel encoder with compatible architecture. The proposed encoder has the advantages of parallel encoding and pipelined operations. Furthermore, it is designed as a configurable encoding structure, which is fully compatible with different base graphs of 5G LDPC. Thus, the encoder architecture has flexible adaptability for various 5G LDPC codes. The proposed encoder was synthesized in a 65 nm CMOS technology. According to the encoder architecture, we implemented nine encoders for distributed lifting sizes of two base graphs. The eperimental results show that the encoder has high performance and significant area-efficiency, which is better than related prior art. This work includes a whole set of encoding algorithm and the compatible encoders, which are fully compatible with different base graphs of 5G LDPC codes. Therefore, it has more flexible adaptability for various 5G application scenarios.


2012 ◽  
Vol 25 (3) ◽  
pp. 370-382
Author(s):  
Virasit Imtawil ◽  
Mongkol Kupimai ◽  
Anan Kruesubthaworn ◽  
Apirat Siritaratiwat ◽  
Anupap Meesomboon
Keyword(s):  

Author(s):  
Fulong Wang ◽  
Ming Zhan ◽  
Qian Zhang ◽  
Hao Tang ◽  
Yunkai Feng ◽  
...  
Keyword(s):  

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