scholarly journals High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

Symmetry ◽  
2021 ◽  
Vol 13 (4) ◽  
pp. 700
Author(s):  
Yufei Zhu ◽  
Zuocheng Xing ◽  
Zerun Li ◽  
Yang Zhang ◽  
Yifan Hu
Keyword(s):  
High Performance ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Cmos Technology ◽  
Area Efficiency ◽  
Prior Art ◽  
New Radio ◽  
High Area ◽  
Significant Area ◽  
Area Efficient

This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible with the 5th generation (5G) new radio (NR). Basing on the algorithm, we propose a high area-efficient parallel encoder with compatible architecture. The proposed encoder has the advantages of parallel encoding and pipelined operations. Furthermore, it is designed as a configurable encoding structure, which is fully compatible with different base graphs of 5G LDPC. Thus, the encoder architecture has flexible adaptability for various 5G LDPC codes. The proposed encoder was synthesized in a 65 nm CMOS technology. According to the encoder architecture, we implemented nine encoders for distributed lifting sizes of two base graphs. The eperimental results show that the encoder has high performance and significant area-efficiency, which is better than related prior art. This work includes a whole set of encoding algorithm and the compatible encoders, which are fully compatible with different base graphs of 5G LDPC codes. Therefore, it has more flexible adaptability for various 5G application scenarios.

scholarly journals A scalable ASIP for BP Polar decoding with multiple code lengths

2018 ◽  
Vol 232 ◽  
pp. 01046
Author(s):  
Wan Qiao ◽  
Dake Liu
Keyword(s):  
Cmos Technology ◽  
Single Instruction Multiple Data ◽  
Instruction Set ◽  
Maximum Throughput ◽  
Specific Instruction ◽  
Area Efficiency ◽  
Multiple Data ◽  
High Area ◽  
Multiple Code ◽  
Application Specific

In this paper, we propose a flexible scalable BP Polar decoding application-specific instruction set processor (PASIP) that supports multiple code lengths (64 to 4096) and any code rates. High throughputs and sufficient programmability are achieved by the single-instruction-multiple-data (SIMD) based architecture and specially designed Polar decoding acceleration instructions. The synthesis result using 65 nm CMOS technology shows that the total area of PASIP is 2.71 mm2. PASIP provides the maximum throughput of 1563 Mbps (for N = 1024) at the work frequency of 400MHz. The comparison with state-of-art Polar decoders reveals PASIP’s high area efficiency.

Performance Analysis of MIA Algorithm for LDPC Codes in near Space Rain Attenuation Channel

2011 ◽  
Vol 148-149 ◽  
pp. 1576-1582
Author(s):  
Yi Dong Su ◽  
Shu Xin Chen ◽  
Hao Wu
Keyword(s):  
Iterative Decoding ◽  
High Performance ◽  
Channel Model ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Rain Attenuation ◽  
Soft Decision ◽  
Decision Algorithm ◽  
Decoding Complexity ◽  
Near Space

According to the influence of grand reflector to the channel, near space Ka-band rain attenuation channel model of area coverage is improved. According to RRWBF algorithm and UMP BP-Based algorithm of LDPC codes, a mixed iterative decoding algorithm is proposed. The algorithm takes advantage of low complexity of hard-decision algorithm and high performance of soft-decision algorithm, so in near space rain attenuation channel, the decoding complexity significantly reduced when bit error rate performance does not decline. Simulation results show that in near space rain attenuation channel, MIA algorithm can reduce decoding complexity by about 30%, compare with the UMP BP-Based algorithm.

Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes

2020 ◽  
pp. 1-13
Author(s):  
Hangxuan Cui ◽  
Fakhreddine Ghaffari ◽  
Khoa Le ◽  
David Declercq ◽  
Jun Lin ◽  
...  
Keyword(s):  
High Performance ◽  
Ldpc Codes ◽  
Area Efficient

scholarly journals Efficient QC-LDPC Encoder for 5G New Radio

Electronics ◽  
2019 ◽  
Vol 8 (6) ◽  
pp. 668 ◽  
Author(s):  
Tram Thi Bao Nguyen ◽  
Tuy Nguyen Tan ◽  
Hanho Lee
Keyword(s):  
Substantial Reduction ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Complexity ◽  
Cmos Technology ◽  
Memory Storage ◽  
Oxide Semiconductor ◽  
Parity Check ◽  
Hardware Complexity ◽  
New Radio ◽  
Encoding Method

This paper presents a novel efficient encoding method and a high-throughput low-complexity encoder architecture for quasi-cyclic low-density parity-check (QC-LDPC) codes for the 5th-generation (5G) New Radio (NR) standard. By storing the quantized value of the permutation information for each submatrix instead of the whole parity check matrix, the required memory storage size is considerably reduced. In addition, sharing techniques are employed to reduce the hardware complexity. The encoding complexity of the proposed method was analyzed, and indicated a substantial reduction in the required area as well as memory storage when compared with existing state-of-the-art encoding approaches. The proposed method requires only 61% gate area, and 11% ROM storage when compared with a similar LDPC encoder using the Richardson–Urbanke method. Synthesis results on TSMC 65-nm complementary metal-oxide semiconductor (CMOS) technology with different submatrix sizes were carried out, which confirmed that the design methodology is flexible and can be adapted for multiple submatrix sizes. For all the considered submatrix sizes, the throughput ranged from 22.1–202.4 Gbps, which sufficiently meets the throughput requirement for the 5G NR standard.

scholarly journals Combining hard and soft decoders for hypergraph product codes

Quantum ◽  
2021 ◽  
Vol 5 ◽  
pp. 432
Author(s):  
Antoine Grospellier ◽  
Lucien Grouès ◽  
Anirudh Krishna ◽  
Anthony Leverrier
Keyword(s):  
High Performance ◽  
Belief Propagation ◽  
Linear Time ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Large Error ◽  
Error Correcting Codes ◽  
Product Codes ◽  
Constant Rate ◽  
Zero Rate

Hypergraph product codes are a class of constant-rate quantum low-density parity-check (LDPC) codes equipped with a linear-time decoder called small-set-flip (SSF). This decoder displays sub-optimal performance in practice and requires very large error correcting codes to be effective. In this work, we present new hybrid decoders that combine the belief propagation (BP) algorithm with the SSF decoder. We present the results of numerical simulations when codes are subject to independent bit-flip and phase-flip errors. We provide evidence that the threshold of these codes is roughly 7.5% assuming an ideal syndrome extraction, and remains close to 3% in the presence of syndrome noise. This result subsumes and significantly improves upon an earlier work by Grospellier and Krishna (arXiv:1810.03681). The low-complexity high-performance of these heuristic decoders suggests that decoding should not be a substantial difficulty when moving from zero-rate surface codes to constant-rate LDPC codes and gives a further hint that such codes are well-worth investigating in the context of building large universal quantum computers.

scholarly journals Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1106
Author(s):  
Vladimir L. Petrović ◽  
Dragomir M. El Mezeni ◽  
Andreja Radošević
Keyword(s):  
Channel Coding ◽  
Parallel Architecture ◽  
Ldpc Codes ◽  
Parity Check ◽  
Case Scenario ◽  
New Radio ◽  
Physical Channel ◽  
Computationally Intensive ◽  
Hardware Processing ◽  
Usage Efficiency

Quasi-cyclic low-density parity-check (QC–LDPC) codes are introduced as a physical channel coding solution for data channels in 5G new radio (5G NR). Depending on the use case scenario, this standard proposes the usage of a wide variety of codes, which imposes the need for high encoder flexibility. LDPC codes from 5G NR have a convenient structure and can be efficiently encoded using forward substitution and without computationally intensive multiplications with dense matrices. However, the state-of-the-art solutions for encoder hardware implementation can be inefficient since many hardware processing units stay idle during the encoding process. This paper proposes a novel partially parallel architecture that can provide high hardware usage efficiency (HUE) while achieving encoder flexibility and support for all 5G NR codes. The proposed architecture includes a flexible circular shifting network, which is capable of shifting a single large bit vector or multiple smaller bit vectors depending on the code. The encoder architecture was built around the shifter in a way that multiple parity check matrix elements can be processed in parallel for short codes, thus providing almost the same level of parallelism as for long codes. The processing schedule was optimized for minimal encoding time using the genetic algorithm. The optimized encoder provided high throughputs, low latency, and up-to-date the best HUE.

scholarly journals Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 516
Author(s):  
Tram Thi Bao Nguyen ◽  
Tuy Nguyen Tan ◽  
Hanho Lee
Keyword(s):  
Wireless Communication ◽  
High Throughput ◽  
Low Complexity ◽  
Ldpc Decoder ◽  
Processor Architectures ◽  
New Radio ◽  
Decoder Architecture ◽  
Check Node ◽  
Information Update ◽  
Wireless Standards

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

MOF/PEDOT/HPMo-based polycomponent hierarchical hollow micro-vesicles for high performance flexible supercapacitors

2021 ◽  
Vol 9 (5) ◽  
pp. 2948-2958
Author(s):  
Bing Wang ◽  
Shuo Liu ◽  
Lin Liu ◽  
Wen-Wei Song ◽  
Yue Zhang ◽  
...  
Keyword(s):  
Electrode Material ◽  
High Performance ◽  
Cycle Stability ◽  
Supercapacitor Electrode ◽  
Flexible Supercapacitors ◽  
High Area

The three-component PCN-224/PEDOT/PMo12 supercapacitor electrode material is designed to offer high area capacitance, good cycle stability and mechanical flexibility.

Sign in / Sign up

Export Citation Format

Share Document