Low-complexity high-rate irregular QC-LDPC codes with applications to PR2 and EPR2 channels

Low-density parity-check (LDPC) codes have the potential for applications in future high throughput optical communications due to their significant error correction capability and the parallel decoding. However, they are not able to satisfy the very low bit error rate (BER) requirement due to the error floor phenomenon. In this paper, we propose a low-complexity iterative decoding scheme for product codes consisting of very high rate outer codes and LDPC codes. The outer codes aim at eliminating the residual error floor of LDPC codes with quite low implementation costs. Furthermore, considering the long simulation time of computer simulation for evaluating very low BER, the hardware platform is built to accelerate the evaluation of the proposed iterative decoding methods. Simultaneously, the fixed-point effects of the decoding algorithms are also be evaluated. The experimental results show that the iterative decoding of the product codes can achieve a quite low bit error rate. The evaluation using field programmable gate array (FPGA) also proves that product codes with LDPC codes and high-rate algebraic codes can achieve a good trade-off between complexity and throughput.

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Low complexity encoding of LDPC codes for high-rate and high-speed communication

2008 First International Conference on Distributed Framework and Applications ◽

10.1109/icdfma.2008.4784435 ◽

2008 ◽

Author(s):

Jeong Ki Kim ◽

S. P. Balakannan ◽

Moon Ho Lee ◽

Chang Joo Kim

Keyword(s):

High Speed ◽

Ldpc Codes ◽

Low Complexity ◽

High Rate

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High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

Symmetry ◽

10.3390/sym13040700 ◽

2021 ◽

Vol 13 (4) ◽

pp. 700

Author(s):

Yufei Zhu ◽

Zuocheng Xing ◽

Zerun Li ◽

Yang Zhang ◽

Yifan Hu

Keyword(s):

High Performance ◽

Ldpc Codes ◽

Low Complexity ◽

Cmos Technology ◽

Area Efficiency ◽

Prior Art ◽

New Radio ◽

High Area ◽

Significant Area ◽

Area Efficient

This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible with the 5th generation (5G) new radio (NR). Basing on the algorithm, we propose a high area-efficient parallel encoder with compatible architecture. The proposed encoder has the advantages of parallel encoding and pipelined operations. Furthermore, it is designed as a configurable encoding structure, which is fully compatible with different base graphs of 5G LDPC. Thus, the encoder architecture has flexible adaptability for various 5G LDPC codes. The proposed encoder was synthesized in a 65 nm CMOS technology. According to the encoder architecture, we implemented nine encoders for distributed lifting sizes of two base graphs. The eperimental results show that the encoder has high performance and significant area-efficiency, which is better than related prior art. This work includes a whole set of encoding algorithm and the compatible encoders, which are fully compatible with different base graphs of 5G LDPC codes. Therefore, it has more flexible adaptability for various 5G application scenarios.

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