A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power

Integration ◽  
2018 ◽  
Vol 60 ◽  
pp. 160-166 ◽  
Author(s):  
Ahmad Karimi ◽  
Abdalhossein Rezai ◽  
Mohammad Mahdi Hajhashemkhani
Keyword(s):  
Low Power ◽  
Leakage Power ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Power Pulse ◽  
Novel Design

Ultra-Low Power Pulse-Triggered CNTFET-Based Flip-Flop

2019 ◽  
Vol 18 ◽  
pp. 756-761
Author(s):  
Ahmad Karimi ◽  
Abdalhossein Rezai ◽  
Mohammad Mahdi Hajhashemkhani
Keyword(s):  
Low Power ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Power Pulse

Energy-efficient data retention in D flip-flops using STT-MTJ

Circuit World ◽  
2020 ◽  
Vol 46 (4) ◽  
pp. 229-241 ◽  
Author(s):  
Kanika Monga ◽  
Nitin Chaturvedi ◽  
S. Gurunarayanan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Leakage Power ◽  
Total Power ◽  
System State ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Content Type ◽  
Total Power Consumption ◽  
Standby Mode

Purpose Emerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. However, it results in a loss of system state, and a considerable amount of energy is required to restore the system state. Conventional state retentive flip-flops have an “Always ON” circuitry, which results in large leakage power consumption, especially during long standby periods. Therefore, this paper aims to explore the emerging non-volatile memory element spin transfer torque-magnetic tunnel junction (STT-MTJ) as one the prospective candidate to obtain a low-power solution to state retention. Design/methodology/approach The conventional D flip-flop is modified by using STT-MTJ to incorporate non-volatility in slave latch. Two novel designs are proposed in this paper, which can store the data of a flip-flip into the MTJs before power off and restores after power on to resume the operation from pre-standby state. Findings A comparison of the proposed design with the conventional state retentive flip-flop shows 100 per cent reduction in leakage power during standby mode with 66-69 per cent active power and 55-64 per cent delay overhead. Also, a comparison with existing MTJ-based non-volatile flip-flop shows a reduction in energy consumption and area overhead. Furthermore, use of a fully depleted-silicon on insulator and fin field-effect transistor substituting a complementary metal oxide semiconductor results in 70-80 per cent reduction in the total power consumption. Originality/value Two novel state-retentive D flip-flops using STT-MTJ are proposed in this paper, which aims to obtain zero leakage power during standby mode.

Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flop

2021 ◽  
Author(s):  
Yugal Maheshwari ◽  
Kleber Stangherlin ◽  
Derek Wright ◽  
Manoj Sachdev
Keyword(s):  
Low Power ◽  
Single Phase ◽  
Low Energy ◽  
Flip Flop ◽  
Ultra Low Power

scholarly journals Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

2019 ◽  
Vol 54 (2) ◽  
pp. 550-559 ◽  
Author(s):  
Yunpeng Cai ◽  
Anand Savanth ◽  
Pranay Prabhat ◽  
James Myers ◽  
Alex S. Weddell ◽  
...  
Keyword(s):  
Low Power ◽  
Single Phase ◽  
Flip Flop ◽  
Ultra Low Power

Ultra-low power subthreshold flip-flop design

2009 ◽  
Author(s):  
Sagi Fisher ◽  
Adam Teman ◽  
Dmitry Vaysman ◽  
Alexander Gertsman ◽  
Orly Yadid-Pecht ◽  
...  
Keyword(s):  
Low Power ◽  
Flip Flop ◽  
Ultra Low Power

Implementation of MHLFF based low power pulse triggered flip flop

2017 ◽  
Vol 7 (1.1) ◽  
pp. 483
Author(s):  
Shreya Verma ◽  
Tunikipati Usharani ◽  
S Iswariya ◽  
Bhavana Godavarthi
Keyword(s):  
Low Power ◽  
Pulse Generator ◽  
Research Paper ◽  
Flip Flop ◽  
Power Pulse

The present research paper proposes to implement a low power pulse-triggered flip-flop. The proposed design is MHLFF (modified hybrid latch flip-flop). In MHLFF method, the pulse generator will be altered concerning illustration inverters what’s more a pasquinade transistor. This technique will be comparative should understood kind about flip flop what’s more it utilizes a static lock structure. Should succeed Most exceedingly bad situation delay issue brought on Eventually Tom's perusing discharging way comprise from claiming three stacked transistor MHLFF may be presented.  We can minimize the power and delay when compared to the existing models i.e, CDFF and SCDFF. The circuit was implementing using Cadence Virtuoso tool in 90-nm and 45-nm technology.

Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms

2014 ◽  
Vol 61 (6) ◽  
pp. 1755-1765 ◽  
Author(s):  
Djaafar Chabi ◽  
Weisheng Zhao ◽  
Erya Deng ◽  
Yue Zhang ◽  
Nesrine Ben Romdhane ◽  
...  
Keyword(s):  
Low Power ◽  
Power Gating ◽  
Flip Flop ◽  
Ultra Low Power
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