A 5-GS/s 10-b 76-mW Time-Interleaved SAR ADC in 28 nm CMOS

2017 ◽  
Vol 64 (7) ◽  
pp. 1673-1683 ◽  
Author(s):  
Jie Fang ◽  
Shankar Thirunakkarasu ◽  
Xuefeng Yu ◽  
Fabian Silva-Rivas ◽  
Chaoming Zhang ◽  
...  
Keyword(s):  
Sar Adc ◽  
Time Interleaved ◽  
28 Nm

A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS

2020 ◽  
pp. 1-12 ◽  
Author(s):  
Athanasios T. Ramkaj ◽  
Juan C. Pena Ramos ◽  
Marcel J. M. Pelgrom ◽  
Michiel S. J. Steyaert ◽  
Marian Verhelst ◽  
...  
Keyword(s):  
Passive Sampling ◽  
Sampling Time ◽  
Sar Adc ◽  
Time Interleaved ◽  
28 Nm

scholarly journals A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (24) ◽  
pp. 3173
Author(s):  
Jingchao Lan ◽  
Danfeng Zhai ◽  
Yongzhen Chen ◽  
Zhekan Ni ◽  
Xingchen Shen ◽  
...  
Keyword(s):  
Power Efficiency ◽  
Low Frequency ◽  
Sar Adc ◽  
Background Calibration ◽  
High Input ◽  
Input Buffer ◽  
Digital Background Calibration ◽  
High Bandwidth ◽  
Time Interleaved ◽  
28 Nm

A 2.5-GS/s 12-bit four-way time-interleaved pipelined-SAR ADC is presented in 28-nm CMOS. A bias-enhanced ring amplifier is utilized as the residue amplifier to achieve high bandwidth and excellent power efficiency compared with a traditional operational amplifier. A high linearity front-end is proposed to alleviate the non-linearity of the diode for ESD protection in the input PAD. The embedded input buffer can suppress the kickback noise at high input frequencies. A blind background calibration based on digital-mixing is used to correct the mismatches between channels. Additionally, an optional neural network calibration is also provided. The prototype ADC achieves a low-frequency SNDR/SFDR of 51.0/68.0 dB, translating a competitive FoMw of 0.48 pJ/conv.-step at 250 MHz input running at 2.5 GS/s.

A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler

2020 ◽  
pp. 1-12
Author(s):  
Wenning Jiang ◽  
Yan Zhu ◽  
Chi-Hang Chan ◽  
Boris Murmann ◽  
Rui Paulo Martins
Keyword(s):  
Sar Adc ◽  
Time Interleaved ◽  
Timing Skew

An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS

2013 ◽  
Author(s):  
E. Janssen ◽  
K. Doris ◽  
A. Zanikopoulos ◽  
A. Murroni ◽  
G. van der Weide ◽  
...  
Keyword(s):  
Sar Adc ◽  
Time Interleaved

scholarly journals A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC

2013 ◽  
Vol 48 (8) ◽  
pp. 1783-1794 ◽  
Author(s):  
Si-Seng Wong ◽  
U-Fat Chio ◽  
Yan Zhu ◽  
Sai-Weng Sin ◽  
Seng-Pan U ◽  
...  
Keyword(s):  
Binary Search ◽  
Sar Adc ◽  
Time Interleaved

A 56-GS/s 8-bit Time-Interleaved ADC With ENOB and BW Enhancement Techniques in 28-nm CMOS

2019 ◽  
Vol 54 (3) ◽  
pp. 821-833 ◽  
Author(s):  
Kexu Sun ◽  
Guanhua Wang ◽  
Qing Zhang ◽  
Salam Elahmadi ◽  
Ping Gui
Keyword(s):  
Interleaved Adc ◽  
Time Interleaved ◽  
28 Nm

A 2-GS/s 8-bit Time-Interleaved SAR ADC for Millimeter-Wave Pulsed Radar Baseband SoC

2017 ◽  
Vol 52 (10) ◽  
pp. 2712-2720 ◽  
Author(s):  
Takuji Miki ◽  
Toshiaki Ozeki ◽  
Jun-ichi Naka
Keyword(s):  
Millimeter Wave ◽  
Sar Adc ◽  
Time Interleaved
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