Extracting RLC Parasitics From a Flexible Electronic Hybrid Assembly Using On-Chip ESD Protection Circuits

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2021.3102103 ◽

2021 ◽

pp. 1-13

Author(s):

Rafid Adnan Khan ◽

Mohammad Muhtady Muhaisin ◽

Gordon W. Roberts

Keyword(s):

Hybrid Assembly ◽

Flexible Electronic ◽

Esd Protection ◽

Protection Circuits ◽

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New design concept for on-chip ESD protection circuits with already-on device in nanoscale CMOS technology

The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. ◽

10.1109/apccas.2004.1413010 ◽

2005 ◽

Author(s):

Ming-Dou Ker ◽

Kuo-Chun Hsu

Keyword(s):

Cmos Technology ◽

Design Concept ◽

Nanoscale Cmos ◽

Esd Protection ◽

Protection Circuits ◽

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On‐chip ESD Protection Circuits – Input Circuitry

The ESD Handbook ◽

10.1002/9781119233091.ch9 ◽

2021 ◽

pp. 363-440

Keyword(s):

Esd Protection ◽

Protection Circuits ◽

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On‐Chip ESD Protection Circuits – ESD Power Clamps

The ESD Handbook ◽

10.1002/9781119233091.ch10 ◽

2021 ◽

pp. 441-489

Keyword(s):

Esd Protection ◽

Protection Circuits ◽

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Complementary substrate-triggered SCR devices for on-chip ESD protection circuits

15th Annual IEEE International ASIC/SOC Conference ◽

10.1109/asic.2002.1158061 ◽

2003 ◽

Author(s):

Ming-Dou Ker ◽

Kuo-Chun Hsu

Keyword(s):

Esd Protection ◽

Protection Circuits ◽

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Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-μm salicided CMOS process

ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) ◽

10.1109/icecs.2001.957754 ◽

2002 ◽

Author(s):

Ming-Dou Ker ◽

Che-Hao Chuang ◽

Wen-Yu Lo

Keyword(s):

Layout Design ◽

Cmos Process ◽

Esd Protection ◽

Protection Circuits ◽

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An Unassisted, Low Trigger-, and High Holding-Voltage SCR (uSCR) for On-Chip ESD-Protection Applications

IEEE Electron Device Letters ◽

10.1109/led.2007.909838 ◽

2007 ◽

Vol 28 (12) ◽

pp. 1120-1122 ◽

Author(s):

Lifang Lou ◽

Juin J. Liou

Keyword(s):

Esd Protection ◽

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P-45: On-Chip ESD Protection Design for UXGA/HDTV LCoS in 0.35-μm CMOS Technology

SID Symposium Digest of Technical Papers ◽

10.1889/1.1830999 ◽

2004 ◽

Vol 35 (1) ◽

pp. 404

Author(s):

Ming-Dou Ker ◽

Shih-Hung Chen ◽

Tang-Kui Tseng

Keyword(s):

Cmos Technology ◽

Esd Protection ◽

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Substrate-triggered technique for on-chip ESD protection design in a 0.18-μm salicided CMOS process

IEEE Transactions on Electron Devices ◽

10.1109/ted.2003.812495 ◽

2003 ◽

Vol 50 (4) ◽

pp. 1050-1057 ◽

Author(s):

Ming-Dou Ker ◽

Tung-Yang Chen

Keyword(s):

Cmos Process ◽

Esd Protection ◽

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Design and Optimization of Vertical SiGe Thyristors for On-Chip ESD Protection

IEEE Transactions on Device and Materials Reliability ◽

10.1109/tdmr.2004.838423 ◽

2004 ◽

Vol 4 (4) ◽

pp. 586-593 ◽

Author(s):

S. Joshi ◽

R. Ida ◽

E. Rosenbaum

Keyword(s):

Design And Optimization ◽

Esd Protection ◽

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Alternative ESD Concepts: On-Chip and Off-Chip ESD Protection Solutions

ESD ◽

10.1002/0470061405.ch10 ◽

2006 ◽

pp. 375-390

Keyword(s):

Esd Protection ◽

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