Substrate-triggered technique for on-chip ESD protection design in a 0.18-μm salicided CMOS process

IEEE Transactions on Electron Devices ◽

10.1109/ted.2003.812495 ◽

2003 ◽

Vol 50 (4) ◽

pp. 1050-1057 ◽

Author(s):

Ming-Dou Ker ◽

Tung-Yang Chen

Keyword(s):

Cmos Process ◽

Esd Protection ◽

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MOS-Bounded Diodes for On-Chip ESD Protection in Deep Submicron CMOS Process

IEICE Transactions on Electronics ◽

10.1093/ietele/e88-c.3.429 ◽

2005 ◽

Vol E88-C (3) ◽

pp. 429-436 ◽

Author(s):

M.-D. KER

Keyword(s):

Deep Submicron ◽

Cmos Process ◽

Esd Protection ◽

Submicron Cmos ◽

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On-chip ESD protection design for GHz RF integrated circuits by using polysilicon diodes in sub-quarter-micron CMOS process

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) ◽

10.1109/vtsa.2001.934529 ◽

2002 ◽

Author(s):

Chyh-Yih Chang ◽

Ming-Dou Ker

Keyword(s):

Integrated Circuits ◽

Cmos Process ◽

Rf Integrated Circuits ◽

Esd Protection ◽

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Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-μm CMOS process

IEEE Transactions on Electron Devices ◽

10.1109/ted.2003.809028 ◽

2003 ◽

Vol 50 (2) ◽

pp. 397-405 ◽

Author(s):

Ming-Dou Ker ◽

Kuo-Chun Hsu

Keyword(s):

Cmos Process ◽

Esd Protection ◽

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On-chip ESD protection design by using polysilicon diodes in CMOS process

IEEE Journal of Solid-State Circuits ◽

10.1109/4.913746 ◽

2001 ◽

Vol 36 (4) ◽

pp. 676-686 ◽

Author(s):

Ming-Dou Ker ◽

Tung-Yang Chen ◽

Tai-Ho Wang ◽

Chung-Yu Wu

Keyword(s):

Cmos Process ◽

Esd Protection ◽

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Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process

IEICE Transactions on Electronics ◽

10.1587/transele.e99.c.590 ◽

2016 ◽

Vol E99.C (5) ◽

pp. 590-596 ◽

Author(s):

Guangyi LU ◽

Yuan WANG ◽

Xing ZHANG

Keyword(s):

Cmos Process ◽

Esd Protection ◽

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MOS-bounded diodes for on-chip ESD protection in a 0.15-μm shallow-trench-isolation salicided CMOS process

2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672) ◽

10.1109/vtsa.2003.1252558 ◽

2004 ◽

Author(s):

Ming-Dou Ker ◽

Kun-Hsien Lin ◽

Che-Hao Chuang

Keyword(s):

Cmos Process ◽

Shallow Trench Isolation ◽

Trench Isolation ◽

Esd Protection ◽

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Active Electrostatic Discharge (ESD) Device for On-Chip ESD Protection in Sub-Quarter-Micron Complementary Metal-Oxide Semiconductor (CMOS) Process

Japanese Journal of Applied Physics ◽

10.1143/jjap.43.l33 ◽

2003 ◽

Vol 43 (1A/B) ◽

pp. L33-L35 ◽

Author(s):

Ming-Dou Ker ◽

Tang-Kui Tseng

Keyword(s):

Metal Oxide ◽

Electrostatic Discharge ◽

Complementary Metal Oxide Semiconductor ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Cmos Process ◽

Esd Protection ◽

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On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) ◽

10.1109/iscas.2002.1010757 ◽

2003 ◽

Author(s):

Ming-Dou Ker ◽

Kuo-Chun Hsu

Keyword(s):

Circuit Design ◽

Cmos Process ◽

Esd Protection ◽

Protection Circuit ◽

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SCR Device With Dynamic Holding Voltage for On-Chip ESD Protection in a 0.25-<tex>$mu hbox m$</tex>Fully Salicided CMOS Process

IEEE Transactions on Electron Devices ◽

10.1109/ted.2004.834904 ◽

2004 ◽

Vol 51 (10) ◽

pp. 1731-1733 ◽

Author(s):

M.-D. Ker ◽

Z.-P. Chen

Keyword(s):

Cmos Process ◽

Esd Protection ◽

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On-Chip HBM and HMM ESD Protection Design for RF Applications in 40-nm CMOS Process

IEEE Transactions on Electron Devices ◽

10.1109/ted.2018.2873768 ◽

2018 ◽

Vol 65 (12) ◽

pp. 5267-5274 ◽

Author(s):

Jie-Ting Chen ◽

Chun-Yu Lin ◽

Rong-Kun Chang ◽

Ming-Dou Ker

Keyword(s):

Cmos Process ◽

Esd Protection ◽

Rf Applications ◽

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