Rail-to-Rail Input Pipelined ADC Incorporating Multistage Signal Mapping

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pp. 558-562 ◽  
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David Gubbins ◽  
Pavan Kumar Hanumolu ◽  
Un-Ku Moon
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scholarly journals A 1.0-V 10-b 30-MS/s 3.4-mW rail-to-rail pipelined ADC using a new front-end MDAC

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Front End ◽  
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VLSI DESIGN OF PIPELINED ADC WITH WIDE RANGE OPERATING TEMPERATURE FOR WAVE APPLICATIONS

2017 ◽  
Vol 6 (2) ◽  
pp. 13
Author(s):  
P LOKESH ◽  
U. SOMALATHA ◽  
S. CHANDANA ◽  
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◽  
...  
Keyword(s):  
Operating Temperature ◽  
Vlsi Design ◽  
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Wide Range

scholarly journals Digital Error Correction Logic for Pipelined ADC Using 1.5Bits/Stage

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Vol 981 ◽  
pp. 032046
Author(s):  
Y. Srikanth ◽  
Ch. Rajendra Prasad ◽  
Koteshwar Rao Danthamala ◽  
P. Ramchandar Rao ◽  
A. Chakradhar
Keyword(s):  
Error Correction ◽  
Pipelined Adc
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