A model for MOS gate stack quality evaluation based on the gate current 1/f noise

2008 9th International Conference on Ultimate Integration of Silicon ◽

10.1109/ulis.2008.4527159 ◽

2008 ◽

Author(s):

P. Magnone ◽

F. Crupi ◽

G. Iannaccone ◽

G. Giusi ◽

C. Pace ◽

...

Keyword(s):

Quality Evaluation ◽

Gate Current ◽

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New insight into MOS gate stack formations on Ge and SiGe from thermodynamics, reaction kinetics and nanoscale engineering

2019 IEEE International Electron Devices Meeting (IEDM) ◽

10.1109/iedm19573.2019.8993522 ◽

2019 ◽

Author(s):

Akira Toriumi ◽

Tomonori Nishimura

Keyword(s):

Reaction Kinetics ◽

Mos Gate ◽

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InGaAs MOS Gate Stack Formation and the MOS Interface Properties

Hyomen Kagaku ◽

10.1380/jsssj.33.628 ◽

2012 ◽

Vol 33 (11) ◽

pp. 628-633

Author(s):

Shinichi TAKAGI ◽

Noriyuki TAOKA ◽

Rena SUZUKI ◽

Masafumi YOKOYAMA ◽

Sang-Hyeon KIM ◽

...

Keyword(s):

Interface Properties ◽

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On the dc and noise properties of the gate current in epitaxial Ge p-channel metal oxide semiconductor field effect transistors with TiN∕TaN∕HfO2∕SiO2 gate stack

Applied Physics Letters ◽

10.1063/1.2916821 ◽

2008 ◽

Vol 92 (16) ◽

pp. 163508 ◽

Author(s):

Debabrata Maji ◽

Felice Crupi ◽

Gino Giusi ◽

Calogero Pace ◽

Eddy Simoen ◽

...

Keyword(s):

Metal Oxide ◽

Field Effect ◽

Field Effect Transistors ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

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Low-thermal-budget MOS gate stack formation using a cluster tool rapid-thermal-processing module

10.1117/12.167369 ◽

1994 ◽

Author(s):

A. M. Bayoumi ◽

J. Montgomery ◽

R. T. Kuehn ◽

F. S. Johnson ◽

John R. Hauser

Keyword(s):

Thermal Processing ◽

Rapid Thermal Processing ◽

Thermal Budget ◽

Processing Module ◽

Low Thermal Budget ◽

Mos Gate ◽

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Properties of Ru/HfxSi1-xOy/Si MOS Gate Stack Structures Grown by MOCVD

ECS Meeting Abstracts ◽

10.1149/ma2005-01/14/650 ◽

2005 ◽

Keyword(s):

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Gate Current Modeling and Optimization of High-k Gate Stack MOSFET Structure in Nano Scale Regime

International Journal of Micro-Nano Scale Transport ◽

10.1260/1759-3093.1.3.253 ◽

2010 ◽

Vol 1 (3) ◽

pp. 253-268

Author(s):

Ashwani Rana ◽

Narottam Chand ◽

Vinod Kapoor

Keyword(s):

Gate Current ◽

Modeling And Optimization ◽

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Design, optimization, and characterization of a low temperature RPECVD MOS gate stack process

[1993] Proceedings of the Tenth Biennial University/Government/Industry Microelectronics Symposium ◽

10.1109/ugim.1993.297054 ◽

2002 ◽

Author(s):

C.G. Parker ◽

C. Silvestre ◽

M. Watkins ◽

R.T. Keuhn ◽

J.R. Hauser

Keyword(s):

Low Temperature ◽

Design Optimization ◽

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Threshold Voltage Engineering by Lanthanide Doping of the MOS Gate Stack

10.1063/1.3033672 ◽

2008 ◽

Author(s):

A. Fet ◽

V. Häublein ◽

H. Ryssel ◽

Edmund G. Seebauer ◽

Susan B. Felch ◽

...

Keyword(s):

Threshold Voltage ◽

Lanthanide Doping ◽

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Gate current modelling through high-k gate stack MOSFET for very-large-scale integration logic circuit analysis

Australian Journal of Electrical & Electronics Engineering ◽

10.7158/e10-856.2012.9.1 ◽

2012 ◽

Vol 9 (1) ◽

Author(s):

AK Rana ◽

N Chand ◽

V Kapoor

Keyword(s):

Large Scale ◽

Logic Circuit ◽

Circuit Analysis ◽

Very Large Scale Integration ◽

Gate Current ◽

High K ◽

Large Scale Integration ◽

Scale Integration ◽

Current Modelling

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MOS gate current characteristics and their implications for lifetime area scaling

Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. ◽

10.1109/essder.2005.1546667 ◽

2005 ◽

Author(s):

S. Kleft ◽

R. Bottini ◽

G. Ghidini

Keyword(s):

Gate Current ◽

Current Characteristics ◽

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