This paper presented a low-power Direct Digital Frequency Synthesizer (DDFS) using non-uniform sine-weighted digital-to-analog convertor (DAC). To avoid the need for a sharp filter to generate signals near and beyond the Nyquist frequency, parallel DACs, which cause to speed relaxation in a single DAC as well, and return-to-zero (RZ) technique were used. To reduce the area and power in parallel DACs, non-uniform sine-weighted DAC design method was proposed. This technique causes to reduce power consumption in DACs up to 48.47%, and nearly the same amount of reduction in the area. Meanwhile, by modifying weights of DAC cells, Gilbert cell, the latter block in DDFS structure, was omitted. Although these proposed methods are quite frequency independent, simulations with MATLAB and Cadence in 0.18[Formula: see text][Formula: see text]m CMOS technology were used to demonstrate those. Then, the designed DDFS with 5-bit frequency resolution could generate different output sine signals with acceptable spurious free dynamic range (SFDR).
Hardware Implementation of 32-Bit High-Speed Direct Digital Frequency Synthesizer
