Hardware Implementation of 32-Bit High-Speed Direct Digital Frequency Synthesizer

The design and implementation of a high-speed direct digital frequency synthesizer are presented. A modified Brent-Kung parallel adder is combined with pipelining technique to improve the speed of the system. A gated clock technique is proposed to reduce the number of registers in the phase accumulator design. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The ROM lookup table (LUT) is partitioned into three 4-bit sub-ROMs based on angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2 : 1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz. These techniques make the direct digital frequency synthesizer an attractive candidate for wireless communication applications.

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Design of DDS Based on FPGA Technology

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.713-715.1031 ◽

2015 ◽

Vol 713-715 ◽

pp. 1031-1033

Author(s):

Wei Jiang ◽

Fang Yuan ◽

Liu Qing Yang

Keyword(s):

High Frequency ◽

Simple Structure ◽

Frequency Synthesizer ◽

Sine Wave ◽

Lookup Table ◽

Frequency Resolution ◽

Signal Frequency ◽

Small Delay ◽

Working Principle ◽

Output Only

This paper introduces the working principle and structure of direct digital frequency synthesizer. This paper select the technology of lookup table to design DDS because it has many advantages such as less consumption hardware resources, simple structure, output only small delay and so on. As a result, signal generator can produce many waveforms with good stability and high frequency resolution. Finally, test showed that the output wave of triangular signal frequency is greater than 1MHz and the highest sine wave frequency is 30MHz, the value of peak to peak is continuously adjustable in 50mV ~ 4V range. The result of study will provide theoretical guidance for the design of DDS.

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A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) ◽

10.1109/iscas.2002.1010718 ◽

2003 ◽

Cited By ~ 7

Author(s):

Byung-Do Yang ◽

Lee-Sup Kim ◽

Hyun-Kyu Yu

Keyword(s):

Low Power ◽

High Speed ◽

Frequency Synthesizer ◽

Digital Frequency ◽

Direct Digital Frequency Synthesizer

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A Low-Power Efficient Direct Digital Frequency Synthesizer Based on New Two-Level Lookup Table

2006 Canadian Conference on Electrical and Computer Engineering ◽

10.1109/ccece.2006.277378 ◽

2006 ◽

Cited By ~ 4

Author(s):

Shu-chung Yi ◽

Kun-tse Lee ◽

Jin-jia Chen ◽

Chien-hung Lin

Keyword(s):

Low Power ◽

Frequency Synthesizer ◽

Lookup Table ◽

Power Efficient ◽

Digital Frequency ◽

Direct Digital Frequency Synthesizer

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A high-speed ROM-less direct digital frequency synthesizer realized by a segmented non-linear DAC

TENCON 2007 - 2007 IEEE Region 10 Conference ◽

10.1109/tencon.2007.4429034 ◽

2007 ◽

Cited By ~ 1

Author(s):

Weng Jun-Hong ◽

Jing-Shing Wen ◽

Chung-Yuan Yang

Keyword(s):

High Speed ◽

Frequency Synthesizer ◽

Digital Frequency ◽

Non Linear ◽

Direct Digital Frequency Synthesizer

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An area efficient memory-less ROM design architecture for direct digital frequency synthesizer

International Journal of Electrical and Computer Engineering (IJECE) ◽

10.11591/ijece.v11i1.pp257-264 ◽

2021 ◽

Vol 11 (1) ◽

pp. 257

Author(s):

Salah Alkurwy ◽

Sawal H. Ali ◽

Md. Shabiul Islam ◽

Faizul Idros

Keyword(s):

Frequency Synthesizer ◽

Logic Gate ◽

Lookup Table ◽

Verilog Hdl ◽

Digital Frequency ◽

Novel Approach ◽

Direct Digital Frequency Synthesizer ◽

A New Technique ◽

Simple Logic ◽

Efficient Memory

This paper introduces a new technique of designing a read-only memory (ROM) circuit, namely; memory-less ROM as a novel approach to designing the ROM lookup table (LUT) circuit for use in a direct digital frequency synthesizer (DDFS). The proposed DDFS design uses the pipelined phase accumulator (PA) based on the kogge-stone (KS) adder. Verilog HDL programming is encoded on the architecture circuit of pipelined PA and contrasted with other PA based on various adders. The obtained results define the KS adder as having good capabilities for improving the throughput. In addition to the quarter symmetry technique, the built memory-less ROM to obtain the quarter sine amplitude waveform is proposed and implemented in the DDFS system. The implementation of the proposed technique replaces the necessary ROM registers (384 D flip-flops) and multiplexers with simple logic gate circuits instead of traditional ROMs. This technique would reduce the area size and cell count by 56% and 32.6% respectively.

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