Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

Author(s):  
A. Gupta ◽  
H. Mertens ◽  
Z. Tao ◽  
S. Demuynck ◽  
J. Bommels ◽  
...  
Keyword(s):  
2008 ◽  
Vol 29 (5) ◽  
pp. 491-493 ◽  
Author(s):  
Xin Sun ◽  
Qiang Lu ◽  
V. Moroz ◽  
H. Takeuchi ◽  
G. Gebara ◽  
...  
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2013 ◽  
Vol 50 (9) ◽  
pp. 3-16 ◽  
Author(s):  
E. J. Nowak
Keyword(s):  

2010 ◽  
Vol 54 (9) ◽  
pp. 855-860 ◽  
Author(s):  
T. Chiarella ◽  
L. Witters ◽  
A. Mercha ◽  
C. Kerner ◽  
M. Rakowski ◽  
...  
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2002 ◽  
Vol 745 ◽  
Author(s):  
J. Raynien Kwo ◽  
Minghwei Hong

ABSTRACTThe ability of controlling the growth and interfaces of ultrathin dielectric films on Si and compound semiconductors by ultrahigh vacuum physical vapor deposition has led to comprehensive studies of gate stacks employing the high κ gate oxide Ga2O3(Gd2O3), and the rare earth oxides Gd2O3 and Y2O3. The epitaxy and the interfaces of Gd2O3 on GaAs, GaN, and Si were characterized with atomic precision, and show strong tendency to conform to the underlying substrate, thus providing insight into the fundamental mechanism for low interfacial state density and effective passivation of GaAs and GaN surfaces. These Gd2O3 and Y2O3 gate stacks of abrupt interfaces and controlled microstructures were employed as a model system to elucidate critical issues of materials integration in CMOS scaling.


Author(s):  
Antoine Cros ◽  
Krunoslav Romanjek ◽  
Dominique Fleury ◽  
Samuel Harrison ◽  
Robin Cerutti ◽  
...  

2019 ◽  
Vol 13 (1) ◽  
pp. 253-262
Author(s):  
Prashant Majhi ◽  
Jungwoo Oh ◽  
Se-Hoon Lee ◽  
Rusty Harris ◽  
Hsing-Huang Tseng ◽  
...  

Author(s):  
Mrunal A. Khaderbad ◽  
V. Ramgopal Rao
Keyword(s):  

Author(s):  
A. Mocuta ◽  
P. Weckx ◽  
S. Demuynck ◽  
D. Radisic ◽  
Y. Oniki ◽  
...  
Keyword(s):  

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