Impact of CMOS Scaling on RF/MMIC Designs

Author(s):  
M.-C. Frank Chang ◽  
Daquan Huang
Keyword(s):  
2008 ◽  
Vol 29 (5) ◽  
pp. 491-493 ◽  
Author(s):  
Xin Sun ◽  
Qiang Lu ◽  
V. Moroz ◽  
H. Takeuchi ◽  
G. Gebara ◽  
...  
Keyword(s):  

2013 ◽  
Vol 50 (9) ◽  
pp. 3-16 ◽  
Author(s):  
E. J. Nowak
Keyword(s):  

2010 ◽  
Vol 54 (9) ◽  
pp. 855-860 ◽  
Author(s):  
T. Chiarella ◽  
L. Witters ◽  
A. Mercha ◽  
C. Kerner ◽  
M. Rakowski ◽  
...  
Keyword(s):  

2002 ◽  
Vol 745 ◽  
Author(s):  
J. Raynien Kwo ◽  
Minghwei Hong

ABSTRACTThe ability of controlling the growth and interfaces of ultrathin dielectric films on Si and compound semiconductors by ultrahigh vacuum physical vapor deposition has led to comprehensive studies of gate stacks employing the high κ gate oxide Ga2O3(Gd2O3), and the rare earth oxides Gd2O3 and Y2O3. The epitaxy and the interfaces of Gd2O3 on GaAs, GaN, and Si were characterized with atomic precision, and show strong tendency to conform to the underlying substrate, thus providing insight into the fundamental mechanism for low interfacial state density and effective passivation of GaAs and GaN surfaces. These Gd2O3 and Y2O3 gate stacks of abrupt interfaces and controlled microstructures were employed as a model system to elucidate critical issues of materials integration in CMOS scaling.


Author(s):  
Antoine Cros ◽  
Krunoslav Romanjek ◽  
Dominique Fleury ◽  
Samuel Harrison ◽  
Robin Cerutti ◽  
...  

2019 ◽  
Vol 13 (1) ◽  
pp. 253-262
Author(s):  
Prashant Majhi ◽  
Jungwoo Oh ◽  
Se-Hoon Lee ◽  
Rusty Harris ◽  
Hsing-Huang Tseng ◽  
...  

Author(s):  
Mrunal A. Khaderbad ◽  
V. Ramgopal Rao
Keyword(s):  

Author(s):  
A. Mocuta ◽  
P. Weckx ◽  
S. Demuynck ◽  
D. Radisic ◽  
Y. Oniki ◽  
...  
Keyword(s):  

2010 ◽  
Vol 2010 (1) ◽  
pp. 000001-000006 ◽  
Author(s):  
Philip Garrou

IC technology, which has traditionally been dominated by dimensional scaling, is facing several technical and economic hurdles as it moves forward. Low K insulation has not been able to meet performance projections, copper traces are becoming more and more resistive, clock rates have been constrained due to thermal issues and multicore processors are demanding major increases in bandwidth and decreases in latency. Economic constraints will also begin limiting the number of IC companies able to develop leading-edge IC designs. Moving past 45 nm digital CMOS scaling will no longer guarantee lower cost and higher performance. All of these issues have crated a “perfect storm scenario” for the widespread adoption of 3D IC technology.


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