SoC Test Data Compression Technique Based on RLE-G

2010 ◽  
Vol 439-440 ◽  
pp. 1595-1600
Author(s):  
Chun Jian Deng ◽  
Liu Wei ◽  
Xi Feng Zheng ◽  
Liang Yang
Keyword(s):  
Data Compression ◽  
Test Data ◽  
Test Time ◽  
Test Data Compression ◽  
Compression Technique ◽  
Current Test ◽  
Soc Test ◽  
Efficient Test ◽  
Data Volume ◽  
Test Vectors

Test data compression has been an effective way to reduce test data volume and test time, as well as to solve automatic test equipment (ATE) memory and bandwidth limitation. We analyze the limitations of current test data compression algorithm and draw on the previous experience to deduce an optimal compression coding model suitable for SoC test data. In addition, in this paper we make full use of the relevance of the test vectors and the advantages of statistical coding to present an efficient test data compression method RLE-G based on the coding model, and give the RLE-G the optimal compression efficiency of the boundary conditions and realization steps. The experimental results for ISCAS 89 benchmark circuits demonstrate RLE-G have the excellent advantages of high compression ratio.

scholarly journals Efficient Test Data Compression for SoC through ASRL with Improved Dictionary based Compression Technique

2019 ◽  
Vol 8 (11) ◽  
pp. 3591-3597
Keyword(s):  
Embedded System ◽  
Data Compression ◽  
Test Data ◽  
Compression Ratio ◽  
Test Data Compression ◽  
Bandwidth Utilization ◽  
Compression Technique ◽  
Memory Size ◽  
Efficient Test ◽  
Effective Manner

Data compression techniques are explored in this paper, through which system memory size gets reduced in an effective manner. The size of the memory is always a key constraint in the embedded system. Larger memory size increases the bandwidth utilization which raises the cost of hardware and data transmission. It is difficult to transfer large data through the network. Data compression encoding technique is utilized to minimize the data size. The redundant character is reduced or encoding the bits in data is done to reduce the data size. The proposed system focused on lossless compression where the original information of the data is available even though the data size is compressed. The data compression is done through a dictionary-based compression algorithm and Alternating Statistical Run Length code (ASRL). In the existing system of ASRL, the compression ratio is about 65.16% and 67.18% for two benchmark circuits S5378 &S9234. The compression ratio of the test data is increased by combining the ASRL and Improved Dictionary-Based compression Technique. The proposed combined technique provides 80.25%& 82.5% compression ratio for two benchmark circuits S5378 &S9234. This reduces the power dissipation problem in the circuit and thereby the area of the circuit gets reduced.

scholarly journals A SoC-IP Core Test Data Compression Scheme based on Error Correcting Hamming Codes

2018 ◽  
Vol 12 (3) ◽  
pp. 933
Author(s):  
Sanjoy Mitra ◽  
Debaprasad Das
Keyword(s):  
Test Data ◽  
Structural Information ◽  
Huffman Coding ◽  
Test Data Compression ◽  
Compression Scheme ◽  
Hamming Codes ◽  
Efficient Test ◽  
Data Volume ◽  
Ip Cores ◽  
Test Vectors

As system-on-chip (SoC) integration is growing very rapidly, increased circuit densities in SoC have lead a radical increase in test data volume and reduction of this large test data volume is one of the biggest challenges in the testing industry. This paper presents an efficient test independent compression scheme primarily based on the error correcting Hamming codes. The scheme operates on the pre-computed test data without the need of structural information of the circuit under test and thus it is applicable for IP cores in SoC. Test vectors are equally sliced into the size of ‘<em>n’</em> bits. Individual slices are treated as a Hamming codeword consisting of ‘<em>p’</em> parity bits and ‘<em>d’</em> data bits (<em>n = d + p)</em> and validity of each codeword is verified. If a valid slice is encountered<em>’</em> data bits prefixed by ‘<em>1’</em> are written to the compressed file, while for a non-valid slice all ‘<em>n’</em> bits preceded by ‘<em>0’</em> are written to the compressed file. Finally, we apply Huffman coding and RLE in order to improve the compression ratio further The efficiency of the proposed hybrid scheme is verified with the experimental outcomes and comparisons to existing compression methods suitable for testing of IP cores.

Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs

2011 ◽  
pp. 434-459
Author(s):  
Anders Larsson ◽  
Urban Ingelsson ◽  
Erik Larsson ◽  
Krishnendu Chakrabarty
Keyword(s):  
Data Compression ◽  
Design Process ◽  
Test Data ◽  
Architecture Design ◽  
Test Data Compression ◽  
Compression Technique ◽  
Test Cost ◽  
Test Execution ◽  
Data Volume ◽  
Test Architecture

Test-data volume and test execution times are both costly commodities. To reduce the cost of test, previous studies have used test-data compression techniques on system-level to reduce the test-data volume or employed test architecture design for module-based SOCs to enable test schedules with low test execution time. Research on combining the two approaches is lacking. Therefore, this chapter studies how core-level test-data compression can be combined with test architecture design to reduce test cost further. The study is conducted in three steps. The first step analyzes how the TAM width influences three test-data compression techniques, namely Selective Encoding, Vector Repeat and the combination of the two. The second step investigates in what order to consider test architecture and test-data compression in the SOC design process to best reduce test cost. It is observed that test architecture design and test-data compression-technique selection should be performed in an integrated process. The third step presents a novel approach to integrate test-data compression-technique selection in the test architecture design process. Experiments on benchmarks with realistic cores show that the integrated approach achieves up to 32% reduction in test cost (7.8% on average) compared to non-integrated test architecture design and test-data compression technique selection.

Test data compression technique based on partial data block reuse in SoC

2010 ◽  
Vol 24 (5) ◽  
pp. 487-493
Author(s):  
Yiming Ouyang ◽  
Xi'e Huang ◽  
Huaguo Liang ◽  
Baosheng Zou
Keyword(s):  
Data Compression ◽  
Test Data ◽  
Data Block ◽  
Test Data Compression ◽  
Compression Technique ◽  
Partial Data
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