Field-programmable gate array implementation of Consultative Committee for Space Data Systems image data compression

2012 ◽  
Vol 6 (1) ◽  
pp. 063551 ◽  
Author(s):  
Chieh-Fu Chang
2015 ◽  
Vol 12 (2) ◽  
Author(s):  
Patria Rachman Hakim ◽  
Abdul Rahman ◽  
Deddy El Amin ◽  
Widya Roza ◽  
Elvira Rahim

Salah satu fungsi sistem Payload Data Handling (PDH) pada sebuah satelit adalah melakukan channel coding untuk data citra satelit. Consultative Committee for Space Data Systems (CCSDS) telah merekomendasikan penggunaan encoder Reed-Solomon (RS) untuk keperluan channel coding tersebut. Untuk dapat merealisasikan transmisi dengan laju data yang tinggi, maka implementasi algoritma encoder RS pada sitem PDH satelit membutuhkan Field Programmable Gate Array (FPGA). Penelitian ini bertujuan untuk merancang modul encoder RS(255,223) berbasis CCSDS dan mengimplementasikan encoder tersebut pada FPGA dengan desain rangkaian yang lebih optimal dibandingkan dengan encoder RS komersial (IP-core). Berdasarkan hasil pengujian yang telah dilakukan, encoder yang dirancang memiliki beberapa kelebihan dalam hal efisiensi gerbang logika yang digunakan dan tingkat kinerja data keluaran yang dihasilkan. Selain itu, pada penelitian ini juga dikembangkan metode encoding paralel yang akan diterapkan pada sistem PDH satelit. Hasil pengujian menunjukkan bahwa dengan menggunakan metode tersebut, data keluaran yang dihasilkan encoder memiliki laju data yang lebih tinggi dan tidak membutuhkan data dummy untuk melengkapi data keluaran. Kedua hasil tersebut diharapkan dapat mendukung pengembangan sistem PDH satelit yang dilakukan di Pusat Teknologi Satelit saat ini.Kata kunci: Channel coding, Encoder Reed-Solomon, PDH, FPGA, CCSDS


2020 ◽  
Vol 37 (5) ◽  
pp. 745-752
Author(s):  
Qizhi Fang ◽  
Yuxuan Liu ◽  
Lili Zhang

Despite its popularity, the hyperspectral image compression algorithm recommended by the Consultative Committee for Space Data Systems (CCSDS) faces a long delay of the feedback loop and complex computations in the modes of band sequential (BSQ) and band interleaved by line (BIL). After analyzing the features of the CCSDS algorithm, this paper proposes a forward prediction method based on the xc7k325tffg9000 field programmable gate array (FPGA) chip (Xilinx Inc.), and adjusts the calculation flow of the CCSDS algorithm, aiming to shorten the time delay in the feedback loop. In addition, full-pipeline construction was implemented on FPGA board to realize real-time processing of data, and dynamic configuration of image parameters. Through functional simulation and off-board test, it is learned that, for the speed-insensitive path, the optimized algorithm can realize the complex operations of the original algorithm with less hardware resources; for hyperspectral image data with an effective input bit width of 12bit, the proposed method can reach a maximum operating frequency of 103MHz, and the data throughput of 103M samples per second (1.237Gbps).


2015 ◽  
Vol 9 (1) ◽  
pp. 097499 ◽  
Author(s):  
Nektarios Kranitis ◽  
Ioannis Sideris ◽  
Antonios Tsigkanos ◽  
Georgios Theodorou ◽  
Antonios Paschalis ◽  
...  

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1234 ◽  
Author(s):  
Elias Machairas ◽  
Nektarios Kranitis

Remote sensing is recognized as a cornerstone monitoring technology. The latest high-resolution and high-speed spaceborne imagers provide an explosive growth in data volume and instrument data rates in the range of several Gbps. This competes with the limited on-board storage resources and downlink bandwidth, making image data compression a mission-critical on-board processing task. The Consultative Committee for Space Data Systems (CCSDS) Image Data Compression (IDC) standard CCSDS-122.0-B-1 is a transform-based 2D image compression algorithm designed specifically for use on-board a space platform. In this paper, we introduce a high-performance architecture for a key-part of the CCSDS-IDC algorithm, the 9/7M Integer Discrete Wavelet Transform (DWT). The proposed parallel architecture achieves 2 samples/cycle while the very deep pipeline enables very high clock frequencies. Moreover, it exploits elastic pipeline principles to provide modularity, latency insensitivity and distributed control. The implementation of the proposed architecture on a Xilinx Kintex Ultrascale XQRKU060 space-grade SRAM FPGA achieves state-of-the-art throughput performance of 831 MSamples/s (13.3 Gbps @ 16bpp) allowing seamless integration with next-generation high-speed imagers and on-board data handling networking technology. To the best of our knowledge, this is the fastest implementation of the 9/7M Integer DWT on a space-grade FPGA, outperforming previous implementations.


2014 ◽  
Vol 2014 ◽  
pp. 1-8
Author(s):  
Jin Li ◽  
Fei Xing ◽  
Ting Sun ◽  
Zheng You

Space multiband CCD camera compression encoder requires low-complexity, high-robustness, and high-performance because of its captured images information being very precious and also because it is usually working on the satellite where the resources, such as power, memory, and processing capacity, are limited. However, the traditional compression approaches, such as JPEG2000, 3D transforms, and PCA, have the high-complexity. The Consultative Committee for Space Data Systems-Image Data Compression (CCSDS-IDC) algorithm decreases the average PSNR by 2 dB compared with JPEG2000. In this paper, we proposed a low-complexity compression algorithm based on deep coupling algorithm among posttransform in wavelet domain, compressive sensing, and distributed source coding. In our algorithm, we integrate three low-complexity and high-performance approaches in a deeply coupled manner to remove the spatial redundant, spectral redundant, and bit information redundancy. Experimental results on multiband CCD images show that the proposed algorithm significantly outperforms the traditional approaches.


2008 ◽  
Author(s):  
Michael Wirthlin ◽  
Brent Nelson ◽  
Brad Hutchings ◽  
Peter Athanas ◽  
Shawn Bohner

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