High-resolution encoding process for an integrated optical analog-to-digital converter

1994 ◽  
Vol 33 (8) ◽  
pp. 2638 ◽  
Author(s):  
David D. Styer
Photonics ◽  
2021 ◽  
Vol 8 (2) ◽  
pp. 52
Author(s):  
Yue Liu ◽  
Jifang Qiu ◽  
Chang Liu ◽  
Yan He ◽  
Ran Tao ◽  
...  

An optical analog-to-digital converter (OADC) scheme with enhanced bit resolution by using a multimode interference (MMI) coupler as optical quantization is proposed. The mathematical simulation model was established to verify the feasibility and to investigate the robustness of the scheme. Simulation results show that 20 quantization levels (corresponding to 4.32 of effective number of bits (ENOB)) are realized by using only 6 channels, which indicates that the scheme requires much fewer quantization channels or modulators to realize the same amount of ENOB. The scheme is robust and potential for integration.


Author(s):  
Eka Fitrah Pribadi ◽  
Rajeev Kumar Pandey ◽  
Paul C.-P. Chao

Abstract A high-resolution, low offset delta-sigma analog to digital converter for detecting photoplethysmography (PPG) signal is presented in this study. The PPG signal is a bio-optical signal incorporated with heart functionality and located in the range of 0.1–10 Hz. The location to get PPG signal is on a pulsating artery. Thus the delta-sigma analog-to-digital (DS ADC) converter is designed specifically in that range. However, the DS ADC circuitry suffers from 1/f noise under 10 Hz frequency range. A chopper based operational amplifier is implemented in DS ADC to push the 1/f noise into high-frequency noise. The dc offset of the operational amplifier is also pushed to the high-frequency region. The DS ADC circuitry consists of a second-order continuous-time delta-sigma modulator. The delta-sigma modulator circuitry is designed and simulated using TSMC 180 nm technology. The continuous-time delta-sigma modulator active area layout is 746μm × 399 μm and fabricated using TSMC 180 nm technology. It operates in 100 Hz bandwidth and 4096 over-sampling ratios. The SFDR of the circuit is above 70 dB. The power consumption of the delta-sigma modulator is 35.61μW. The simulation is performed in three different kinds of corner, SS, TT, and FF corner, to guarantee the circuitry works in different conditions.


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