This paper proposes a low-loss and high-isolation transformer (TF)-based mm-wave single-pole double-throw (SPDT) switch. The center-tapped technique is employed at the secondary coil of TF to improve isolation performance. The TF is implemented with the metals in redistribution layers (RDLs) in integrated fan-out (InFO) wafer level packaging technology to obtain low insertion loss (IL) and small chip size as the TF usually dominates the area of SPDT. The control device of the SPDT is realized in 40[Formula: see text]nm bulk CMOS process. The simulated result shows the proposed SPDT achieves a minimum IL of 1.34[Formula: see text]dB and the IL is less than 2.2[Formula: see text]dB at 24–31[Formula: see text]GHz. The isolations are better than 27[Formula: see text]dB between two double-throw ports and better than 20[Formula: see text]dB between single-pole and double-throw ports, respectively. The proposed SPDT has a compact silicon size of 220[Formula: see text][Formula: see text] (with PADs) and its return losses are better than [Formula: see text]9[Formula: see text]dB at 24–31[Formula: see text]GHz and. This work explores a new chip-package co-design method for the SPDT and may have some guidance for the co-design of SPDT and antenna in package (AiP).
Low-Loss Single and Differential Semi-Coaxial Interconnects in Standard CMOS Process
