A Pipeline Architecture For Real-Time Connected Components Labeling

Author(s):  
James S. J. Lee ◽  
C. Lin
2002 ◽  
Vol 02 (03) ◽  
pp. 481-499
Author(s):  
JANE YOU ◽  
DAVID ZHANG

This paper presents a new approach to smart sensor system design for real-time remote sensing. A combination of techniques for image analysis and image compression is investigated. The proposed algorithms include: (1) a fractional discrimination function for image analysis, (2) a comparison of effective algorithms for image compression, (3) a pipeline architecture for parallel image classification and compression on-board satellites, and (4) a task control strategy for mapping image computing models to hardware processing elements. The efficiency and accuracy of the proposed techniques are demonstrated throughout system simulation.


2015 ◽  
Vol 35 (2) ◽  
pp. 0210001
Author(s):  
于潇宇 Yu Xiaoyu ◽  
郭玉波 Guo Yubo ◽  
陈刚 Chen Gang ◽  
叶东 Ye Dong

Author(s):  
Vicky Zheng ◽  
Ahmet Erdem Sariyuce ◽  
Jaroslaw Zola

AbstractWith the emergence of portable DNA sequencers, such as Oxford Nanopore Technology MinION, metagenomic DNA sequencing can be performed in real-time and directly in the field. However, because metagenomic DNA analysis is computationally and memory intensive, and the current methods are designed for batch processing, the current metagenomic tools are not well suited for mobile devices.In this paper, we propose a new memory-efficient method to identify Operational Taxonomic Units (OTUs) in metagenomic DNA streams. Our method is based on finding connected components in overlap graphs constructed over a real-time stream of long DNA reads as produced by MinION platform. We propose an efficient algorithm to maintain connected components when an overlap graph is streamed, and show how redundant information can be removed from the stream by transitive closures. Through experiments on simulated and real-world metagenomic data, we demonstrate that the resulting solution is able to recover OTUs with high precision while remaining suitable for mobile computing devices.


Sensors ◽  
2019 ◽  
Vol 19 (4) ◽  
pp. 804 ◽  
Author(s):  
Sagar Shelke ◽  
Baris Aksanli

Convergence of Machine Learning, Internet of Things, and computationally powerful single-board computers has boosted research and implementation of smart spaces. Smart spaces make predictions based on historical data to enhance user experience. In this paper, we present a low-cost, low-energy smart space implementation to detect static and dynamic human activities that require simple motions. We use low-resolution (4 × 16) and non-intrusive thermal sensors to collect data. We train six machine learning algorithms, namely logistic regression, naive Bayes, support vector machine, decision tree, random forest and artificial neural network (vanilla feed-forward) on the dataset collected in our lab. Our experiments reveal a very high static activity detection rate with all algorithms, where the feed-forward neural network method gives the best accuracy of 99.96%. We also show how data collection methods and sensor placement plays an important role in the resulting accuracy of different machine learning algorithms. To detect dynamic activities in real time, we use cross-correlation and connected components of thermal images. Our smart space implementation, with its real-time properties, can be used in various domains and applications, such as conference room automation, elderly health-care, etc.


Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 241
Author(s):  
Hau Ngo ◽  
Ryan Rakvic ◽  
Randy Broussard ◽  
Robert Ives ◽  
Matthew Carothers

Real-time support for an iris recognition algorithm is a considerable challenge for a portable system that is commonly used in the field. In this paper, an efficient parallel and pipeline architecture design for the feature extraction and template matching processes in the Ridge Energy Direction (RED) algorithm for iris recognition is presented. Several techniques used in the proposed architecture design to reduce the computational complexity while supporting a high performance capability include (i) a circle approximation method for the iris unwrapping process, (ii) a parallel design with an on-chip buffer for 2D convolution in the feature extraction process, and (iii) an approximation method for log2 and inverse-log2 conversion in the template matching process. Performance analysis shows that the proposed architecture achieves a speedup of 881 times compared to the conventional method. The proposed design can be integrated with an embedded microprocessor to realize a complete system-on-chip solution for a portable iris recognition system.


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