HANDLING EDGE LISTS IN 2D VECTOR GRAPHICS HARDWARE

2012 ◽  
Vol 21 (03) ◽  
pp. 1250022
Author(s):  
SANG-WOO SEO ◽  
YONG-LUO SHEN ◽  
KWAN-YOUNG KIM ◽  
HYEONG-CHEOL OH
Keyword(s):  
Memory Access ◽  
External Memory ◽  
Graphics Hardware ◽  
Portable Devices ◽  
Hardware Accelerator ◽  
Two Dimensional ◽  
Vector Graphics ◽  
Internal Memory ◽  
Edge List ◽  
Handling Method

In rendering two-dimensional (2D) vector graphics, edge lists are often so large that their handling hinders the desired operation of portable devices. This paper proposes and evaluates an efficient edge-list handling method for a 2D vector graphics hardware accelerator. The proposed method selects edges that span the next scanline from among those spanning the current scanline and stores them in a small list in the internal memory. An edge list is assigned to each scanline and it stores only those edges that have not appeared in previous edge lists. Given that most active edges span only a few scanlines, the internal list can be small and implemented in the accelerator, whereas the edge lists are held in the external memory. Experimental results show that the proposed method can reduce external memory access by 23.4%–76.6% for the benchmark images considered compared to the prior methods.

FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access

2021 ◽  
Author(s):  
Jian Meng ◽  
Shreyas Kolala Venkataramanaiah ◽  
Chuteng Zhou ◽  
Patrick Hansen ◽  
Paul Whatmough ◽  
...  
Keyword(s):  
Neural Networks ◽  
Deep Neural Networks ◽  
Memory Access ◽  
External Memory

scholarly journals A-019 Predictors of Memory Strategy Use in Healthy Older Adults

2020 ◽  
Vol 35 (6) ◽  
pp. 809-809
Author(s):  
Pizzonia K ◽  
Suhr J
Keyword(s):  
Older Adults ◽  
Memory Performance ◽  
Verbal Learning ◽  
Strategy Use ◽  
Community Dwelling ◽  
External Memory ◽  
Memory Ability ◽  
Memory Strategies ◽  
Internal Memory ◽  
Memory Strategy

Abstract Objectives Older adults often use memory strategies to assist with age-associated memory changes, and interventions targeting successful memory strategy use may promote independence. However, individuals vary in their use of memory strategies. We investigated individual difference factors involved in memory strategy use in older adults. Method As part of a larger study on stress and aging, 123 healthy community-dwelling adults over the age of 50 completed various assessments. The present analyses included 91 participants (54% female, mean age 60.80, SD = 8.75) who had completed all measures of interest. Reported external and internal memory strategy use and anxiety about memory ability were measured by the Metamemory in Adulthood (MIA) questionnaire. Psychological variables were measured by the Geriatric Depression Scale, Perceived Stress Scale, and MIA. Memory and working memory performance were assessed using the RBANS, Auditory-Verbal Learning Test, and Auditory Consonant Trigrams. Results Within the context of our model, we found that education (p = .036) and anxiety about memory performance (p = .010) predicted internal memory strategy use, while gender (p = .011), education (p < .001), and anxiety about memory ability (p = .011) predicted external memory strategy use. None of the other variables were related to memory strategy use. Conclusions Though cross-sectional in nature, our results have implications for understanding successful memory strategy use. Regarding demographics, female gender and higher education predicted external memory strategy use, while only education predicted internal memory strategy use. Also, anxiety about memory performance predicted the use of internal and external memory strategies rather than objective memory performance.

scholarly journals TOPOLOGY-PRESERVING WATERMARKING OF VECTOR GRAPHICS

2014 ◽  
Vol 24 (01) ◽  
pp. 61-86 ◽  
Author(s):  
STEFAN HUBER ◽  
MARTIN HELD ◽  
PETER MEERWALD ◽  
ROLAND KWITT
Keyword(s):  
Input Data ◽  
Two Dimensional ◽  
Statistical Features ◽  
Embedding Capacity ◽  
Vector Graphics ◽  
Line Segments ◽  
Circular Arcs ◽  
Straight Line ◽  
Watermark Embedding ◽  
Topological Correctness

Watermarking techniques for vector graphics dislocate vertices in order to embed imperceptible, yet detectable, statistical features into the input data. The embedding process may result in a change of the topology of the input data, e.g., by introducing self-intersections, which is undesirable or even disastrous for many applications. In this paper we present a watermarking framework for two-dimensional vector graphics that employs conventional watermarking techniques but still provides the guarantee that the topology of the input data is preserved. The geometric part of this framework computes so-called maximum perturbation regions (MPR) of vertices. We propose two efficient algorithms to compute MPRs based on Voronoi diagrams and constrained triangulations. Furthermore, we present two algorithms to conditionally correct the watermarked data in order to increase the watermark embedding capacity and still guarantee topological correctness. While we focus on the watermarking of input formed by straight-line segments, one of our approaches can also be extended to circular arcs. We conclude the paper by demonstrating and analyzing the applicability of our framework in conjunction with two well-known watermarking techniques.

Design of External Memory Based on the C8051F02x Microcomputer

2013 ◽  
Vol 722 ◽  
pp. 64-67
Author(s):  
Zhi Jing Liu
Keyword(s):  
External Memory ◽  
Address Space ◽  
Internal Memory ◽  
External Data ◽  
Memory Address ◽  
Data Memory ◽  
Address Data ◽  
On Chip

The C8051F02x microcomputer and its saving structure are introduced, I/O function expanding and connecting are analyzed for its data. The exterior data and the structure of the memory are elaborated with the technique expanding request. Access or expansion of external data memory, external memory interfaces (EMIF). Its data memory address space can be flexibly implemented by the on-chip internal memory can be extended to chip memory. EMIF can be configured as address / data multiplexed or non-multiplexed mode. When big capacity FLASH memorizer is needed, this paper provides a realistic design and methodology for microcomputer and string big capacity FLASH of total line, through the setup and analysis of the SPI of the C8051F02x MCU inner part.

scholarly journals A General Lower Bound on the I/O-Complexity of Comparison-based Algorithms

1992 ◽  
Vol 21 (407) ◽  
Author(s):  
Lars Arge ◽  
Mikael Knudsen ◽  
Kirsten Larsen
Keyword(s):  
Lower Bound ◽  
Lower Bounds ◽  
External Memory ◽  
Optimal Algorithms ◽  
Internal Memory

We show a relationship between the number of comparisons and the number of I/O operations needed to solve a given problem. We work in a model, where the permitted operations are l/O-operations and comparisons of two records in internal memory. An I/O- operation swaps <em>B</em> records between external memory and the internal memory (capable of holding <em>M</em> records). An algorithm for this model is called an I/O-algorithm. The main result of this paper is the following: Given an I/O-algorithm that solves an n-record problem P_n using I/O(bar{x}) I/O's on the input bar{x}, there exists an ordinary comparison algorithm that uses no more than <em>n</em> logB + I/O(bar{x}) € T_{merge}(M-B, B) comparisons on input bar{x}. T_{merge}(n, m) denotes the number of comparisons needed to merge two sorted lists of size n and m, respectively. We use the result to show lower bounds on the number of I/O-operations needed to solve the problems of sorting, removing duplicates from a multiset and determining the mode (the most frequently occurring element in a multiset). Aggarwal and Vitter have shown that the sorting bound is tight. We show the same result for the two other problems, by providing optimal algorithms.

Image Compression By Speck With Reduced Memory

2015 ◽  
Vol 4 (2) ◽  
Author(s):  
Amanat Ali ◽  
Amir Athar Khan ◽  
Sanawer Alam ◽  
N. R. Kidwai
Keyword(s):  
Memory Access ◽  
Access Time ◽  
Portable Devices ◽  
State Table ◽  
Set Partitions ◽  
Dynamic Memory ◽  
Coding Efficiency ◽  
Linked List ◽  
Image Coder ◽  
Linked Lists

Reduced memory set partitioned embedded block (SPECK) image coder is proposed in this paper large run–time memory is required by the original SPECK algorithm due to use of linked lists, so it is unsuitable for memory constrained portable devices. In the proposed algorithm SPECK coder successfully replace the linked lists by fixed length state tables or markers, to keep track of set partitions and encoded information. The proposed algorithm neither uses any linked list nor any state table, therefore completely eliminating the use of any dynamic memory at the time of its execution. This also reduces the memory access time, thereby making it faster than the original SPECK, while retaining the embedded property and having coding efficiency close to original SPECK.

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