A Classification and Evaluation Framework for NoC Mapping Strategies

2016 ◽  
Vol 26 (02) ◽  
pp. 1730001 ◽  
Author(s):  
Toubaline Nesrine ◽  
Bennouar Djamel ◽  
Mahdoum Ali
Keyword(s):  
Network On Chip ◽  
Evaluation Framework ◽  
Challenging Problem ◽  
Chip Design ◽  
Networks On Chip ◽  
Systems On Chip ◽  
Target Architecture ◽  
On Chip ◽  
The Moment ◽  
The Impact

Network on Chip (NoC) is a new communication medium used for systems-on-chip (SoCs). In an SoC, the placement of the communicating elements across the network has an impact on system performance. Such a placing is called the MAPPING phase in networks on chip design process. Many approaches dealing with the mapping phase have been proposed but selecting the best technique for a given NoC remains a challenging problem. This paper attempts to provide an answer to this issue. It motivates and presents a definition and a classification according to some criteria: (i) the algorithms used for solving the mapping problem, (ii) the moment in which the mapping is executed, (iii) the impact of combining mapping with other phases during NoC design and (iv) the target architecture.

scholarly journals Network-On-Chip Topology Generation and Analysis For Transaction-Based Systems-on-Chip

2021 ◽  
Author(s):  
Victor. Dumitriu
Keyword(s):  
Design Method ◽  
Prediction Method ◽  
Network On Chip ◽  
Network Resources ◽  
Case Scenario ◽  
Worst Case ◽  
Networks On Chip ◽  
Analysis And Design ◽  
Systems On Chip ◽  
On Chip

The Network-on-Chip concept is emerging as a promising new method of addressing the communication requirements of complex Systems-on-Chip. However, network design at this level must take into consideration the specific communication protocols of on-chip components. This thesis presents a topology analysis and design method for networks-on-chip based on the transaction-oriented protocols common to on-chip systems. The generated topologies target the latency of critical links in the system, while the analysis method can predict the degree of contention in a system prior to the simulation phase. The proposed topologies are tested using various applications, including and MPEG4 Decoder, and are found to perform the same or better than regular topologies, while using less network resources. The contention prediction method is found to be accurate to within 27% in the worst case scenario.

scholarly journals Network-On-Chip Topology Generation and Analysis For Transaction-Based Systems-on-Chip

2021 ◽  
Author(s):  
Victor. Dumitriu
Keyword(s):  
Design Method ◽  
Prediction Method ◽  
Network On Chip ◽  
Network Resources ◽  
Case Scenario ◽  
Worst Case ◽  
Networks On Chip ◽  
Analysis And Design ◽  
Systems On Chip ◽  
On Chip

The Network-on-Chip concept is emerging as a promising new method of addressing the communication requirements of complex Systems-on-Chip. However, network design at this level must take into consideration the specific communication protocols of on-chip components. This thesis presents a topology analysis and design method for networks-on-chip based on the transaction-oriented protocols common to on-chip systems. The generated topologies target the latency of critical links in the system, while the analysis method can predict the degree of contention in a system prior to the simulation phase. The proposed topologies are tested using various applications, including and MPEG4 Decoder, and are found to perform the same or better than regular topologies, while using less network resources. The contention prediction method is found to be accurate to within 27% in the worst case scenario.

Network-on-Chip Design for Gigascale Systems-on-Chip

2005 ◽  
pp. 21-1-21-19
Author(s):  
Luca Benini ◽  
Davide Bertozzi ◽  
Giovanni De Micheli
Keyword(s):  
Network On Chip ◽  
Chip Design ◽  
Systems On Chip ◽  
On Chip

scholarly journals A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 183
Author(s):  
Jose Ricardo Gomez-Rodriguez ◽  
Remberto Sandoval-Arechiga ◽  
Salvador Ibarra-Delgado ◽  
Viktor Ivan Rodriguez-Abdala ◽  
Jose Luis Vazquez-Avila ◽  
...  
Keyword(s):  
Single Chip ◽  
Synthesis Time ◽  
Networks On Chip ◽  
Data Dependencies ◽  
Layered Architecture ◽  
Systems On Chip ◽  
Challenges And Opportunities ◽  
Computing Platforms ◽  
On Chip ◽  
Many Core

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

Building a multi-FPGA-based emulation framework to support networks-on-chip design and verification

2010 ◽  
Vol 97 (10) ◽  
pp. 1241-1262 ◽  
Author(s):  
Yangfan Liu ◽  
Peng Liu ◽  
Yingtao Jiang ◽  
Mei Yang ◽  
Kejun Wu ◽  
...  
Keyword(s):  
Support Networks ◽  
Chip Design ◽  
Networks On Chip ◽  
On Chip

FoToNoC: A Folded Torus-Like Network-on-Chip Based Many-Core Systems-on-Chip in the Dark Silicon Era

2017 ◽  
Vol 28 (7) ◽  
pp. 1905-1918 ◽  
Author(s):  
Lei Yang ◽  
Weichen Liu ◽  
Weiwen Jiang ◽  
Mengquan Li ◽  
Peng Chen ◽  
...  
Keyword(s):  
Network On Chip ◽  
Dark Silicon ◽  
Systems On Chip ◽  
On Chip ◽  
Many Core
Sign in / Sign up

Export Citation Format

Share Document