FoToNoC: A Folded Torus-Like Network-on-Chip Based Many-Core Systems-on-Chip in the Dark Silicon Era

2017 ◽  
Vol 28 (7) ◽  
pp. 1905-1918 ◽  
Author(s):  
Lei Yang ◽  
Weichen Liu ◽  
Weiwen Jiang ◽  
Mengquan Li ◽  
Peng Chen ◽  
...  
Keyword(s):  
Network On Chip ◽  
Dark Silicon ◽  
Systems On Chip ◽  
On Chip ◽  
Many Core

scholarly journals A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 183
Author(s):  
Jose Ricardo Gomez-Rodriguez ◽  
Remberto Sandoval-Arechiga ◽  
Salvador Ibarra-Delgado ◽  
Viktor Ivan Rodriguez-Abdala ◽  
Jose Luis Vazquez-Avila ◽  
...  
Keyword(s):  
Single Chip ◽  
Synthesis Time ◽  
Networks On Chip ◽  
Data Dependencies ◽  
Layered Architecture ◽  
Systems On Chip ◽  
Challenges And Opportunities ◽  
Computing Platforms ◽  
On Chip ◽  
Many Core

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

scholarly journals Near-Optimal Thermal Monitoring Framework for Many-Core Systems-on-Chip

2015 ◽  
Vol 64 (11) ◽  
pp. 3197-3209 ◽  
Author(s):  
Juri Ranieri ◽  
Alessandro Vincenzi ◽  
Amina Chebira ◽  
David Atienza ◽  
Martin Vetterli
Keyword(s):  
Thermal Monitoring ◽  
Systems On Chip ◽  
Monitoring Framework ◽  
On Chip ◽  
Many Core

A Novel Hybrid Cache Coherence with Global Snooping for Many-core Architectures

2022 ◽  
Vol 27 (1) ◽  
pp. 1-31
Author(s):  
Sri Harsha Gade ◽  
Sujay Deb
Keyword(s):  
Lower Energy ◽  
Cache Coherence ◽  
Network On Chip ◽  
Highly Efficient ◽  
Wireless Links ◽  
Coherence Protocols ◽  
High Area ◽  
On Chip ◽  
Many Core ◽  
Clustered Network

Cache coherence ensures correctness of cached data in multi-core processors. Traditional implementations of existing protocols make them unscalable for many core architectures. While snoopy coherence requires unscalable ordered networks, directory coherence is weighed down by high area and energy overheads. In this work, we propose Wireless-enabled Share-aware Hybrid (WiSH) to provide scalable coherence in many core processors. WiSH implements a novel Snoopy over Directory protocol using on-chip wireless links and hierarchical, clustered Network-on-Chip to achieve low-overhead and highly efficient coherence. A local directory protocol maintains coherence within a cluster of cores, while coherence among such clusters is achieved through global snoopy protocol. The ordered network for global snooping is provided through low-latency and low-energy broadcast wireless links. The overheads are further reduced through share-aware cache segmentation to eliminate coherence for private blocks. Evaluations show that WiSH reduces traffic by and runtime by , while requiring smaller storage and lower energy as compared to existing hierarchical and hybrid coherence protocols. Owing to its modularity, WiSH provides highly efficient and scalable coherence for many core processors.

A Fault-Tolerant Deflection Routing for Network-on-Chip

2016 ◽  
Vol 26 (03) ◽  
pp. 1750037 ◽  
Author(s):  
Xiaofeng Zhou ◽  
Lu Liu ◽  
Zhangming Zhu
Keyword(s):  
Fault Tolerant ◽  
Network On Chip ◽  
Deflection Routing ◽  
Core System ◽  
Routing Schemes ◽  
Routing Performance ◽  
Layout Area ◽  
On Chip ◽  
Many Core ◽  
Redundant Fault

Network-on-Chip (NoC) has become a promising design methodology for the modern on-chip communication infrastructure of many-core system. To guarantee the reliability of traffic, effective fault-tolerant scheme is critical to NoC systems. In this paper, we propose a fault-tolerant deflection routing (FTDR) to address faults on links and router by redundancy technique. The proposed FTDR employs backup links and a redundant fault-tolerant unit (FTU) at router-level to sustain the traffic reliability of NoC. Experimental results show that the proposed FTDR yields an improvement of routing performance and fault-tolerant capability over the reported fault-tolerant routing schemes in average flit deflection rate, average packet latency, saturation throughput and reliability by up to 13.5%, 9.8%, 10.6% and 17.5%, respectively. The layout area and power consumption are increased merely 3.5% and 2.6%.

Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip

2013 ◽  
Author(s):  
Michael Dimopoulos ◽  
Yi Gang ◽  
Mounir Benabdenbi ◽  
Lorena Anghel ◽  
Nacer-Eddine Zergainoh ◽  
...  
Keyword(s):  
Fault Tolerant ◽  
Adaptive Routing ◽  
Systems On Chip ◽  
On Chip ◽  
Many Core
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