Amplitude Control Analysis of a Four-Wing Chaotic Attractor, its Electronic Circuit Designs and Microcontroller-Based Random Number Generator

2017 ◽  
Vol 26 (12) ◽  
pp. 1750190 ◽  
Author(s):  
Akif Akgul ◽  
Chunbiao Li ◽  
Ihsan Pehlivan

An exhaustive analysis of a four-wing chaotic system is presented in this paper. It is proved that the evolution range of some variables can be modulated easily by one coefficient of a cross product term. An amplitude-adjustable chaotic circuit is designed, which shows a good agreement with the theoretical analysis. Also, in this paper a microcontroller-based random number generator (RNG) was designed with a nonlinear four-wing chaotic system. RNG studies of the current time have been usually carried out with complicated structures that are costly and difficult to use in real time implementations and that require so much energy consumption. On the other hand, in this paper, as opposed to the disadvantages mentioned here, a microcontroller-based RNG was designed with a four-wing chaotic system (also discussed in the paper) and this was introduced to literature. Microcontroller-based random numbers that passed randomness tests will be available for use in many fields in real life, particularly in encryption.

2004 ◽  
Vol 14 (11) ◽  
pp. 3995-4008 ◽  
Author(s):  
WEIGUANG YAO ◽  
PEI YU ◽  
CHRISTOPHER ESSEX

In most published chaos-based communication schemes, the system's parameters used as a key could be intelligently estimated by a cracker based on the fact that information about the key is contained in the chaotic carrier. In this paper, we will show that the least significant digits (LSDs) of a signal from a chaotic system can be so highly random that the system can be used as a random number generator. Secure communication could be built between the synchronized generators nonetheless. The Lorenz system is used as an illustration.


2015 ◽  
Vol 25 (02) ◽  
pp. 1550021
Author(s):  
Ramazan Yeniçeri ◽  
Selçuk Kilinç ◽  
Müştak E. Yalçin

Chaotic systems have been used in random number generation, owing to the property of sensitive dependence on initial conditions and hence the possibility to produce unpredictable signals. Within the types of chaotic systems, those which are defined by only one delay-differential equation are attractive due to their simple model. On the other hand, it is possible to synchronize to the future states of a time-delay chaotic system by anticipating synchronization. Therefore, random number generator (RNG), which employs such a system, might not be immune to the attacks. In this paper, attack on a chaos-based random number generator using anticipating synchronization is investigated. The considered time-delay chaotic system produces binary signals, which can directly be used as a source of RNG. Anticipating synchronization is obtained by incorporating other systems appropriately coupled to the original one. Quantification of synchronization is given by the bit error between the streams produced by the original and coupled systems. It is shown that the bit streams generated by the original system can be anticipated by the coupled systems beforehand.


2005 ◽  
Vol 72 (1) ◽  
Author(s):  
Massimo Falcioni ◽  
Luigi Palatella ◽  
Simone Pigolotti ◽  
Angelo Vulpiani

Author(s):  
Mangal Deep Gupta ◽  
R. K. Chauhan

This paper introduces an FPGA implementation of a pseudo-random number generator (PRNG) using Chen’s chaotic system. This paper mainly focuses on the development of an efficient VLSI architecture of PRNG in terms of bit rate, area resources, latency, maximum length sequence, and randomness. First, we analyze the dynamic behavior of the chaotic trajectories of Chen’s system and set the parameter’s value to maintain low hardware design complexity. A circuit realization of the proposed PRNG is presented using hardwired shifting, additions, subtractions, and multiplexing schemes. The benefit of this architecture, all the binary multiplications (except [Formula: see text] and [Formula: see text] operations are performed using hardwired shifting. Moreover, the generated sequences pass all the 15 statistical tests of NIST, while it generates pseudo-random numbers at a uniform clock rate with minimum hardware complexity. The proposed architecture of PRNG is realized using Verilog HDL, prototyped on the Virtex-5 FPGA (XC5VLX50T) device, and its analysis has been done using the Matlab tool. Performance analysis confirms that the proposed Chen chaotic attractor-based PRNG scheme is simple, secure, and hardware efficient, with high potential to be adopted in cryptography applications.


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