2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
Latest Publications

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9781728193960

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100 MHz Random Number Generator Design Using Interleaved Metastable NAND/NOR Latches*

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) ◽

10.1109/apccas50809.2020.9301684 ◽

2020 ◽

Author(s):

Chua-Chin Wang ◽

Shao-Wei Lu

Keyword(s):

Random Number ◽

Random Number Generator ◽

Number Generator ◽

Generator Design

Graph Saliency Network: Using Graph Convolution Network on Saliency Detection

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) ◽

10.1109/apccas50809.2020.9301708 ◽

2020 ◽

Author(s):

Heng-Sheng Lin ◽

Jian-Jiun Ding ◽

Jin-Yu Huang

Keyword(s):

Saliency Detection

An Energy Operating System Adaptive for The Sustainable And Green Energy

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) ◽

10.1109/apccas50809.2020.9301701 ◽

2020 ◽

Author(s):

Yen-Bor Lin ◽

Chih-Chieh Ma ◽

Chong-Cheng Hsu ◽

Ting-Chia Ou ◽

Tsung-Chieh Cheng ◽

...

Keyword(s):

Operating System ◽

Green Energy

Performance Analysis of Non-Profiled Side Channel Attacks Based on Convolutional Neural Networks

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) ◽

10.1109/apccas50809.2020.9301673 ◽

2020 ◽

Author(s):

Ngoc-Tuan Do ◽

Van-Phuc Hoang ◽

Van-Sang Doan

Keyword(s):

Neural Networks ◽

Performance Analysis ◽

Convolutional Neural Networks ◽

Side Channel ◽

Side Channel Attacks

Dynamic Reduction of Power Consumption in Direct-RF Sampling Receivers with Variable Decimation

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) ◽

10.1109/apccas50809.2020.9301704 ◽

2020 ◽

Author(s):

Yuka Nakamatsu ◽

Takao Kihara

Keyword(s):

Power Consumption ◽

Rf Sampling

Sub-Sampling Phase-Locked Loop with Ultra-mini Dead Zone For Locking Time Reduction

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) ◽

10.1109/apccas50809.2020.9301713 ◽

2020 ◽

Author(s):

Yeqing Wang ◽

Zhouchen Ma ◽

Yan Liu ◽

Jian Zhao ◽

Lei Zhang ◽

...

Keyword(s):

Dead Zone ◽

Phase Locked Loop ◽

Time Reduction

Digital Phase Estimation through an I/Q Approach for Angle of Arrival Full-Hardware Localization

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) ◽

10.1109/apccas50809.2020.9301691 ◽

2020 ◽

Author(s):

Antonello Florio ◽

Gianfranco Avitabile ◽

Giuseppe Coviello

Keyword(s):

Phase Estimation ◽

Angle Of Arrival ◽

Digital Phase

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) ◽

10.1109/apccas50809.2020.9301648 ◽

2020 ◽

Keyword(s):

A 72-nW 440-mV Time Register Using Stacked-NMOS-Switched Gated Delay Cell in Biomedical Applications

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) ◽

10.1109/apccas50809.2020.9301716 ◽

2020 ◽

Author(s):

Guowei Chen ◽

Dang Cong Bui ◽

Xinyang Yu ◽

Md. Zahidul Islam ◽

Atsuki Kobayashi ◽

...

Keyword(s):

Biomedical Applications ◽

Delay Cell

Capacitive recombination calibration method to improve the performance of SAR ADC

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) ◽

10.1109/apccas50809.2020.9301689 ◽

2020 ◽

Author(s):

Hua Fan ◽

Xinjie Wu ◽

Quanyuan Feng ◽

Ke Zhang ◽

Jia Zhang

Keyword(s):

Calibration Method ◽

Sar Adc

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

100 MHz Random Number Generator Design Using Interleaved Metastable NAND/NOR Latches*

Graph Saliency Network: Using Graph Convolution Network on Saliency Detection

An Energy Operating System Adaptive for The Sustainable And Green Energy

Performance Analysis of Non-Profiled Side Channel Attacks Based on Convolutional Neural Networks

Dynamic Reduction of Power Consumption in Direct-RF Sampling Receivers with Variable Decimation

Sub-Sampling Phase-Locked Loop with Ultra-mini Dead Zone For Locking Time Reduction

Digital Phase Estimation through an I/Q Approach for Angle of Arrival Full-Hardware Localization

[APCCAS 2020 Copyright notice]

A 72-nW 440-mV Time Register Using Stacked-NMOS-Switched Gated Delay Cell in Biomedical Applications

Capacitive recombination calibration method to improve the performance of SAR ADC

Export Citation Format

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

100 MHz Random Number Generator Design Using Interleaved Metastable NAND/NOR Latches*

Graph Saliency Network: Using Graph Convolution Network on Saliency Detection

An Energy Operating System Adaptive for The Sustainable And Green Energy

Performance Analysis of Non-Profiled Side Channel Attacks Based on Convolutional Neural Networks

Dynamic Reduction of Power Consumption in Direct-RF Sampling Receivers with Variable Decimation

Sub-Sampling Phase-Locked Loop with Ultra-mini Dead Zone For Locking Time Reduction

Digital Phase Estimation through an I/Q Approach for Angle of Arrival Full-Hardware Localization

[APCCAS 2020 Copyright notice]

A 72-nW 440-mV Time Register Using Stacked-NMOS-Switched Gated Delay Cell in Biomedical Applications

Capacitive recombination calibration method to improve the performance of SAR ADC

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
Latest Publications