Joint Effects of Aging and Process Variations on Soft Error Rate of Nano-Scale Digital Circuits

Soft errors have always been a concern in the design of digital circuits. As technology down-scales toward Nanometer sizes, emergence of aging effects, process variations, and Multiple Event Transients (METs) has made the soft error rate (SER) estimation of digital circuits very challenging. This paper intends to characterize the challenges by investigating the cross effects of theses issues in overall SER of a circuit. To this regard, we employ a simulation-based SER estimation approach in which the aging effect, process variations and METs are jointly considered in our fault injection process. In our simulation-based SER estimation approach, a statistical gate delay model is used. The fault injection results into ISCAS85 circuit benchmark reveal that the SER estimation without taking into account the aging effects, the process variations, and METs is significantly inaccurate.

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Gate Resizing for Soft Error Rate Reduction in Nano-scale Digital Circuits Considering Process Variations

2015 Euromicro Conference on Digital System Design ◽

10.1109/dsd.2015.103 ◽

2015 ◽

Cited By ~ 2

Author(s):

Mohsen Raji ◽

Behnam Ghavami ◽

Hossein Pedram

Keyword(s):

Error Rate ◽

Digital Circuits ◽

Process Variations ◽

Soft Error ◽

Rate Reduction ◽

Soft Error Rate ◽

Nano Scale ◽

Gate Resizing

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Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs)

2011 Design, Automation & Test in Europe ◽

10.1109/date.2011.5763020 ◽

2011 ◽

Cited By ~ 37

Author(s):

M Fazeli ◽

S N Ahmadian ◽

S G Miremadi ◽

H Asadi ◽

M B Tahoori

Keyword(s):

Error Rate ◽

Digital Circuits ◽

Soft Error ◽

Soft Error Rate ◽

Rate Estimation

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Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs

Microelectronics Reliability ◽

10.1016/j.microrel.2014.07.100 ◽

2014 ◽

Vol 54 (9-10) ◽

pp. 2344-2348 ◽

Cited By ~ 9

Author(s):

F.L. Kastensmidt ◽

J. Tonfat ◽

T. Both ◽

P. Rech ◽

G. Wirth ◽

...

Keyword(s):

Error Rate ◽

Voltage Scaling ◽

Soft Error ◽

Aging Effects ◽

Soft Error Rate

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SOFT ERROR RATE ESTIMATION FOR COMBINATIONAL LOGIC IN PRESENCE OF SINGLE EVENT MULTIPLE TRANSIENTS

Journal of Circuits System and Computers ◽

10.1142/s0218126614500911 ◽

2014 ◽

Vol 23 (06) ◽

pp. 1450091 ◽

Cited By ~ 14

Author(s):

RAMIN RAJAEI ◽

MAHMOUD TABANDEH ◽

MAHDI FAZELI

Keyword(s):

Error Rate ◽

Radiation Effects ◽

Fault Injection ◽

Estimation Method ◽

Accurate Method ◽

Vlsi Circuits ◽

Soft Error ◽

Accurate Estimation ◽

Fast Method ◽

Soft Error Rate

Fast and accurate estimation of soft error rate in VLSI circuits is an essential step in a soft error tolerant ASIC design. In order to have a cost effective protection against radiation effects in combinational logics, an accurate and fast method for identification of most susceptive gates and paths is needed. In this paper, an efficient, fast and accurate method for soft error propagation probability (SEPP) estimation is presented and its performance is evaluated. This method takes into account all three masking factors in multi cycles. It also considers multiple event transients as a new challenge in soft error tolerant VLSI circuit design. Compared with Monte Carlo (MC) simulation-based fault injection method, our SEPP estimation method has a high level of accuracy (with less than 2% difference) while offering 1000× speedup as compared with MC-based simulation.

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