Gate Resizing for Soft Error Rate Reduction in Nano-scale Digital Circuits Considering Process Variations

2015 ◽  
Author(s):  
Mohsen Raji ◽  
Behnam Ghavami ◽  
Hossein Pedram
Keyword(s):  
Error Rate ◽  
Digital Circuits ◽  
Process Variations ◽  
Soft Error ◽  
Rate Reduction ◽  
Soft Error Rate ◽  
Nano Scale ◽  
Gate Resizing

Joint Effects of Aging and Process Variations on Soft Error Rate of Nano-Scale Digital Circuits

2020 ◽  
pp. 2150012
Author(s):  
Mohammad Sajjad Aghadadi ◽  
Mahdi Fazeli ◽  
Hakem Beitollahi
Keyword(s):  
Error Rate ◽  
Digital Circuits ◽  
Fault Injection ◽  
Process Variations ◽  
Aging Effect ◽  
Soft Error ◽  
Delay Model ◽  
Aging Effects ◽  
Soft Error Rate ◽  
Simulation Based

Soft errors have always been a concern in the design of digital circuits. As technology down-scales toward Nanometer sizes, emergence of aging effects, process variations, and Multiple Event Transients (METs) has made the soft error rate (SER) estimation of digital circuits very challenging. This paper intends to characterize the challenges by investigating the cross effects of theses issues in overall SER of a circuit. To this regard, we employ a simulation-based SER estimation approach in which the aging effect, process variations and METs are jointly considered in our fault injection process. In our simulation-based SER estimation approach, a statistical gate delay model is used. The fault injection results into ISCAS85 circuit benchmark reveal that the SER estimation without taking into account the aging effects, the process variations, and METs is significantly inaccurate.

Output remapping technique for critical paths soft-error rate reduction

2010 ◽  
Vol 4 (4) ◽  
pp. 325-333 ◽  
Author(s):  
Q. Ding ◽  
H. Yang ◽  
Y. Wang ◽  
H. Wang ◽  
R. Luo
Keyword(s):  
Error Rate ◽  
Soft Error ◽  
Rate Reduction ◽  
Soft Error Rate ◽  
Critical Paths

Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion

2009 ◽  
Vol 25 (2-3) ◽  
pp. 197-207 ◽  
Author(s):  
Mihir R. Choudhury ◽  
Quming Zhou ◽  
Kartik Mohanram
Keyword(s):  
Error Rate ◽  
Soft Error ◽  
Circuit Optimization ◽  
Rate Reduction ◽  
Soft Error Rate ◽  
Filter Insertion

Accurate SER Estimation by Transform Matrix Analysis for Fault Tolerant Circuits Design

2010 ◽  
Vol 121-122 ◽  
pp. 87-92
Author(s):  
Chang Hong Yu
Keyword(s):  
Error Rate ◽  
Design Methodology ◽  
Fault Tolerant ◽  
Soft Error ◽  
Error Tolerance ◽  
Digital Systems ◽  
Matrix Analysis ◽  
Soft Error Rate ◽  
Nano Scale ◽  
Transform Matrix

As the transistor sizes continue to shrink, quantum effects will significantly affect the circuit behavior. The inherent unreliability of nano-electronics will have significantly impact on the way of circuits design, so defects and faults of nano-scale circuit technologies have to be taken into account early in the design of digital systems. Fault-tolerant architectures may become a necessity to ensure that the underlying circuit could function properly. In CAD software, a same logic can be made out with different circuits but different design methodology can reach different soft error tolerance ability, so we must find a way to estimate the error rate of the circuit efficiently to make the design more fault tolerant. In this paper, a new way to fault tolerance design in nano-scale circuit by accurate soft error rate (SER) estimation is proposed. Transform matrix is used for SER computation and a design criteria is then proposed. Simulation results show that the proposed transform matrix model is effective for nano-scale circuits and the criteria delivered is suitable CAD tools development in nano-system design.

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