Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations

2017 ◽  
Vol 25 (1) ◽  
pp. 247-260 ◽  
Author(s):  
Mohsen Raji ◽  
Behnam Ghavami
Keyword(s):  
Error Rate ◽  
Process Variations ◽  
Soft Error ◽  
Gate Sizing ◽  
Combinational Circuits ◽  
Rate Reduction ◽  
Soft Error Rate

Output remapping technique for critical paths soft-error rate reduction

2010 ◽  
Vol 4 (4) ◽  
pp. 325-333 ◽  
Author(s):  
Q. Ding ◽  
H. Yang ◽  
Y. Wang ◽  
H. Wang ◽  
R. Luo
Keyword(s):  
Error Rate ◽  
Soft Error ◽  
Rate Reduction ◽  
Soft Error Rate ◽  
Critical Paths

Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion

2009 ◽  
Vol 25 (2-3) ◽  
pp. 197-207 ◽  
Author(s):  
Mihir R. Choudhury ◽  
Quming Zhou ◽  
Kartik Mohanram
Keyword(s):  
Error Rate ◽  
Soft Error ◽  
Circuit Optimization ◽  
Rate Reduction ◽  
Soft Error Rate ◽  
Filter Insertion
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