Real-Time Implementation of MAD-Based RFI Excision on FPGA

2019 ◽  
Vol 08 (01) ◽  
pp. 1940006 ◽  
Author(s):  
Kaushal D. Buch ◽  
Kishor Naik ◽  
Swapnil Nalawade ◽  
Shruti Bhatporia ◽  
Yashwant Gupta ◽  
...  
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
Signal To Noise Ratio ◽  
Radio Frequency Interference ◽  
Challenging Problem ◽  
Signal To Noise ◽  
Absolute Deviation ◽  
Field Programmable ◽  
Wideband Radio ◽  
Robust Variant

Radio Frequency Interference (RFI) excision in wideband radio telescope receivers is gaining significance due to increasing levels of manmade RFI and operation outside the protected radio astronomy bands. The effect of RFI on astronomical data can be significantly reduced through real-time excision. In this paper, Median Absolute Deviation (MAD) is used for excising signals corrupted by strong impulsive interference. MAD estimation requires recursive median calculation which is a computationally challenging problem for real-time excision. This challenge is addressed by implementation of a histogram-based technique for MAD computation. The architecture is developed and optimized for Field Programmable Gate Array (FPGA) implementation. The design of a more robust variant of MAD called Median-of-MAD (MoM) is described. The architecture of MAD and MoM techniques and subsequent optimization allows for four RFI excision blocks on a single Xilinx Virtex-5 FPGA. These techniques have been tested on the GMRT wideband backend (GWB) processing a maximum of 400[Formula: see text]MHz bandwidth and the results show significant improvement in the signal-to-noise ratio (SNR).

Towards Real-Time Impulsive RFI Mitigation for Radio Telescopes

2016 ◽  
Vol 05 (04) ◽  
pp. 1641018 ◽  
Author(s):  
Kaushal D. Buch ◽  
Shruti Bhatporia ◽  
Yashwant Gupta ◽  
Swapnil Nalawade ◽  
Aditya Chowdhury ◽  
...  
Keyword(s):  
Real Time ◽  
Signal To Noise Ratio ◽  
Wide Band ◽  
Radio Frequency Interference ◽  
Radio Telescopes ◽  
Signal To Noise ◽  
Absolute Deviation ◽  
Time Threshold ◽  
Filtering Technique ◽  
Estimation And Filtering

Radio Frequency Interference (RFI) is a growing concern for contemporary radio telescopes. This paper describes techniques for real-time threshold-based detection and filtering of broadband and narrowband RFI for the correlator and beamformer chains of a telescope back-end, with specific applications to the upgraded Giant Meterwave Radio Telescope (uGMRT). The Median Absolute Deviation (MAD) estimator is used for robust estimation of dispersion of the received signal in temporal and spectral domains. Results from the tests carried out for the GMRT wide-band backend (GWB) using this technique show 10 dB improvement in the signal-to-noise ratio. MAD-based estimation and filtering was also found to be useful for filtering beamformer data. The RFI filtering technique demonstrated in this paper will find applications in other radio telescopes as well as receivers for digital communication and passive radiometry.

NON-RECURSIVE COMPUTATION OF 8 × 8 2D DCT FOR HIGH ACCURACY AND LOW AREA

2014 ◽  
Vol 23 (10) ◽  
pp. 1450143 ◽  
Author(s):  
VIJAY K. SHARMA ◽  
K. K. MAHAPATRA ◽  
UMESH C. PATI
Keyword(s):  
Field Programmable Gate Array ◽  
Signal To Noise Ratio ◽  
Vlsi Architecture ◽  
High Accuracy ◽  
Low Power Consumption ◽  
Signal To Noise ◽  
Direct Computation ◽  
Low Area ◽  
Field Programmable ◽  
Recursive Computation

This paper presents non-recursive computation equation for 8 × 8 two-dimensional (2D) discrete cosine transform (DCT) along with novel VLSI architecture for direct computation of DCT without transposition memory. All intermediate operations are performed in non-fraction format. Being non-recursive and all intermediate calculations free of fractions, the proposed architecture has excellent accuracy in terms of peak signal-to-noise ratio (PSNR). The architecture is implemented in 0.18-μm CMOS standard cell technology library and prototyped in Field programmable gate array (FPGA) technology for the silicon validation. Implementation result shows that it has low power consumption and low area as compared to the available architectures of 2D DCT. To further increase the accuracy of computations, hardware overhead is very less as only one register and a multiplier bit-widths need to be changed.

scholarly journals Stego on FPGA: An IWT Approach

2014 ◽  
Vol 2014 ◽  
pp. 1-9 ◽  
Author(s):  
Balakrishnan Ramalingam ◽  
Rengarajan Amirtharajan ◽  
John Bosco Balaguru Rayappan
Keyword(s):  
Field Programmable Gate Array ◽  
Signal To Noise Ratio ◽  
Signal To Noise ◽  
Secret Data ◽  
Encrypted Data ◽  
Space Filling Curve ◽  
Field Programmable ◽  
Integer Wavelet ◽  
Filling Curve ◽  
Reconfigurable Hardware Architecture

A reconfigurable hardware architecture for the implementation of integer wavelet transform (IWT) based adaptive random image steganography algorithm is proposed. The Haar-IWT was used to separate the subbands namely, LL, LH, HL, and HH, from8×8pixel blocks and the encrypted secret data is hidden in the LH, HL, and HH blocks using Moore and Hilbert space filling curve (SFC) scan patterns. Either Moore or Hilbert SFC was chosen for hiding the encrypted data in LH, HL, and HH coefficients, whichever produces the lowest mean square error (MSE) and the highest peak signal-to-noise ratio (PSNR). The fixated random walk’s verdict of all blocks is registered which is nothing but the furtive key. Our system took 1.6 µs for embedding the data in coefficient blocks and consumed 34% of the logic elements, 22% of the dedicated logic register, and 2% of the embedded multiplier on Cyclone II field programmable gate array (FPGA).

Real-time signal processing in field programmable gate array based digital gamma-ray spectrometer

2020 ◽  
Vol 91 (10) ◽  
pp. 104707
Author(s):  
Yinyu Liu ◽  
Hao Xiong ◽  
Chunhui Dong ◽  
Chaoyang Zhao ◽  
Quanfeng Zhou ◽  
...  
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
Field Programmable Gate Array ◽  
Gamma Ray ◽  
Time Signal ◽  
Gamma Ray Spectrometer ◽  
Field Programmable ◽  
Gate Array ◽  
Real Time Signal Processing

The Design and Implementation of Parallel Distributed Algorithm FIR Filter Based on FPGA

2012 ◽  
Vol 571 ◽  
pp. 534-537
Author(s):  
Bao Feng Zhang ◽  
De Hu Man ◽  
Jun Chao Zhu
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
Field Programmable Gate Array ◽  
Distributed Algorithm ◽  
Design Method ◽  
Fir Filter ◽  
Experimental Results ◽  
Linear Phase ◽  
Design And Implementation ◽  
Field Programmable

The article proposed a new method for implementing linear phase FIR filter based on FPGA. For the key to implementing the FIR filter on FPGA—multiply-add operation, a parallel distributed algorithm was presented, which is based on LUT. The designed file was described with VHDL and realized on Altera’s field programmable gate array (FPGA), giving the design method. The experimental results indicated that the system can run stably at 120MHz or more, which can meet the requirements of signal processing for real-time.

A Real-Time Processing System Based on Field Programmable Gate Array for Infrared Image

2009 ◽  
Vol 36 (2) ◽  
pp. 307-311
Author(s):  
罗凤武 Luo Fengwu ◽  
王利颖 Wang Liying ◽  
涂霞 Tu Xia ◽  
陈厚来 Chen Houlai
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
Infrared Image ◽  
Processing System ◽  
Real Time Processing ◽  
Time Processing ◽  
Field Programmable ◽  
Gate Array

scholarly journals Series Wound DC Motor Simulation Applying MATLAB SIMULINK and LabVIEW Control Design and Simulation Module

2019 ◽  
Vol 48 (1) ◽  
pp. 65-69
Author(s):  
Gusztáv Áron Sziki ◽  
Kornél Sarvajcz ◽  
Attila Szántó ◽  
Tamás Mankovits
Keyword(s):  
Real Time ◽  
Direct Current ◽  
Field Programmable Gate Array ◽  
Supply Voltage ◽  
Control Design ◽  
Driving Simulation ◽  
Motor Simulation ◽  
Resistance Torque ◽  
Field Programmable ◽  
Hardware Platforms

In our previous publication a model for series wound direct current (SWDC) motors was described and a simulation program was presented which is based on the above model and was developed in MATLAB environment. In the publication mentioned above, the measurement process of the parameters (bearing resistance torque, electric resistances, dynamic inductances) of the SWDC motor was also described. From the parameters the program calculates the current intensity, rpm and torque of the motor as a function of time. The recent publication is about the realization of the above program applying the Control Design and Simulation Module of NI LabVIEW. This module enables the adjustment of input parameters (e.g. supply voltage) during the running of the program, thus the realization of real time driving simulation. In addition, among others, it can be applied with data acquisition, GPIB, CAN, and FPGA (field-programmable gate array) hardware platforms of National Instruments.

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