A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems

2005 ◽  
Author(s):  
Giuseppe Ascia ◽  
Vincenzo Catania ◽  
Maurizio Palesi ◽  
Davide Patti
Keyword(s):  
Embedded Systems ◽  
System Level ◽  
Trade Offs ◽  
Power Trade

ANALYSIS AND TOOLS FOR THE DESIGN OF VLIW EMBEDDED SYSTEMS IN A MULTI-OBJECTIVE SCENARIO

2007 ◽  
Vol 16 (05) ◽  
pp. 819-846
Author(s):  
VINCENZO CATANIA ◽  
MAURIZIO PALESI ◽  
DAVIDE PATTI
Keyword(s):  
Embedded Systems ◽  
Instruction Scheduling ◽  
Design Flow ◽  
System Level ◽  
Instruction Level Parallelism ◽  
Accurate Estimation ◽  
Subsequent Stage ◽  
Multi Objective ◽  
Trade Offs ◽  
Starting Point

The use of Application-Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to implement. Architectures based on Very Long Instruction Word (VLIW) have found fertile ground in multimedia electronic appliances thanks to their ability to exploit high degrees of Instruction Level Parallelism (ILP) with a reasonable trade-off in complexity and silicon costs. In this case the ASIP specialization involves a complex interaction between hardware- and software-related issues. In this paper we propose tools and methodologies to cope efficiently with this complexity from a multi-objective perspective. We present EPIC-Explorer, an open platform for estimation and system-level exploration of an EPIC/VLIW architecture. We first analyze the possible design objectives, showing that it is necessary, given the fundamental role played by the VLIW compiler in instruction scheduling, to evaluate the appropriateness of ILP-oriented compilation on a case-by-case basis. Then, in the architecture exploration phase, we will use a multi-objective genetic approach to obtain a set of Pareto-optimal configurations. Finally, by clustering the configurations thus obtained, we extract those representing possible trade-offs between the objectives, which are used as a starting point for evaluation via more accurate estimation models at a subsequent stage in the design flow.

System level power-performance trade-offs in embedded systems using voltage and frequency scaling of off-chip buses and memory

2002 ◽  
Author(s):  
Kiran Puttaswamy ◽  
Kyu-Won Choi ◽  
Jun Cheol Park ◽  
Vincent J. Mooney ◽  
Abhijit Chatterjee ◽  
...  
Keyword(s):  
Embedded Systems ◽  
System Level ◽  
Power Performance ◽  
Frequency Scaling ◽  
Trade Offs

AND-OR-XOR NETWORK SYNTHESIS WITH AREA-POWER TRADE-OFF

2011 ◽  
Vol 20 (06) ◽  
pp. 1019-1035 ◽  
Author(s):  
SAMBHU NATH PRADHAN ◽  
M. TILAK KUMAR ◽  
SANTANU CHATTOPDHYAY
Keyword(s):  
Boolean Function ◽  
Solution Space ◽  
Leakage Power ◽  
Total Power ◽  
Synthesis Process ◽  
Network Synthesis ◽  
Trade Off ◽  
Delay Performance ◽  
Trade Offs ◽  
Power Trade

In this paper, a heuristic based on genetic algorithm to realize multi-output Boolean function as three-level AND-OR-XOR network performing area power trade-off is presented. All the previous works dealt with the minimization of number of product terms only in the two sum-of-product-expressions representing a Boolean function during AND-OR-XOR network synthesis. To the best of knowledge this is the first ever effort to incorporate total power, that is, dynamic and leakage power along with the area (in terms of number of product terms) during three-level AND-OR-XOR networks synthesis. The synthesis process, without changing the delay performance results in lesser number of product terms compared to those reported in the literature. It also enumerates the trade-offs present in the solution space for different weights associated with area, dynamic power, and leakage power of the resulting circuit.

Framework Design Supporting QoS-Power Trade-Offs for Heterogeneous Networked Systems

2008 ◽  
pp. 71-80
Author(s):  
Christos Antonopoulos ◽  
Evangelos Topalis ◽  
Aggeliki Prayati ◽  
Spilios Giannoulis ◽  
Antonis Athanasopoulos ◽  
...  
Keyword(s):  
Networked Systems ◽  
Framework Design ◽  
Trade Offs ◽  
Power Trade

Optimized System-Level Design Methods for NoC-Based Many Core Embedded Systems

2014 ◽  
pp. 150-179
Author(s):  
Haoyuan Ying ◽  
Klaus Hofmann ◽  
Thomas Hollstein
Keyword(s):  
Embedded Systems ◽  
Design Optimization ◽  
Optimization Methods ◽  
Design Methods ◽  
System Level ◽  
System Level Design ◽  
Level Design ◽  
On Chip ◽  
Many Core

Due to the growing demand on high performance and low power in embedded systems, many core architectures are proposed the most suitable solutions. While the design concentration of many core embedded systems is switching from computation-centric to communication-centric, Network-on-Chip (NoC) is one of the best interconnect techniques for such architectures because of the scalability and high communication bandwidth. Formalized and optimized system-level design methods for NoC-based many core embedded systems are desired to improve the system performance and to reduce the power consumption. In order to understand the design optimization methods in depth, a case study of optimizing many core embedded systems based on 3-Dimensional (3D) NoC with irregular vertical link distribution topology through task mapping, core placement, routing, and topology generation is demonstrated in this chapter. Results of cycle-accurate simulation experiments prove the validity and efficiency of the design methods. Specific to the case study configuration, in maximum 60% vertical links can be saved while maintaining the system efficiency in comparison to full vertical link connection 3D NoCs by applying the design optimization methods.

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