Routing Optimization Based on OSPF in Multi-Layer Satellite Network

Multi-layer satellite network has become a hot spot for its wider coverage and higher bandwidth level. However, due to the frequent link changes and complexity of network, it is hard to find out a mechanism to handle well on long delay and high packet loss level. This paper proposes an optimized OSPF protocol called OOWLP to eliminate unnecessary routing convergence to optimize the packet loss level and delay ultimately. Link plan table, which records link contacting plan, will be used to update the link state database periodically so that we can eliminate the flooding procedure caused by scheduled link changes. On the other hand, Constrained Shortest Path First (CSPF) will be used to get business differentiated routes in multi-layer satellite network to optimized the throughput capacity in congestion scenario. We divide the sending packets into different businesses and get the routes for each business with longer duration limited by remaining bandwidth. Simulation results show that in normal scenario, average packet loss rate and delay performance are improved 17.42%, 51.44ms respectively, average packet loss rate and throughput capacity performance are optimized 79.05%, 9.81Mbps respectively in congestion scenario compared to standard OSPF. As a result, the proposed mechanism is able to shorten the average delay and lower the packet loss level in multi-layer satellite network.

Broadband Design of Acoustic Metasurfaces for the Stabilization of a Mach 4 Boundary Layer Flow

A piecewise acoustic metasurface is designed to suppress the first mode while marginally amplifying the Mack second mode in a Mach 4 flat-plate boundary layer (BL) flow. The results of linear stability theory (LST) and the eN method demonstrate the stabilization effect and transition delay performance, respectively. However, the direct numerical simulation (DNS) results indicate that the designed broadband acoustic metasurface actually weakly excites the first mode with a slightly larger fluctuating pressure amplitude at the surface, which is in contrast to the analysis of LST. The discrepancies are found to lie in the ‘roughness’ effect caused by the recirculation zones inside the microslits and the alternating expansion and compression waves induced at the slit edges, which significantly amplifies the first mode. For further clarification of the competitive mechanism between the acoustic stabilization and ‘roughness’ destabilization effects of metasurfaces on the first mode, a carefully designed metasurface is installed at the maximum growth rate region, which excites the first mode on the metasurface but inhibits its development downstream.

Design and Implementation of Low Power and Area Efficient Architecture for High Performance ALU

Digital Signal Processors (DSP) have a ubiquitous presence in almost all civil and military signal processing applications, including mission critical environments like nuclear reactors, process control etc. Arithmetic and Logic units (ALU), being the heart of any digital signal processor, play critical and decisive roles in achieving the required parameter benchmarks and the overall efficiency and robustness of the digital signal processor. State of the art research has shown successful traction with the performance requirements of critical Multiply-Accumulate (MAC) parameters, like reduced power consumption, small electronic real estate footprint and reduction in delay with the associated design complexity. Judicious placement of its building blocks, namely, the truncated multiplier and half-sum carry generation-sum carry generation (HSCG-SCG) adder in the architectural design of ALU and the type of adder and multiplier circuits selected are the core decisions that decide the overall performance of the ALU. To overcome the drawback and to improve the performance further, this work proposes a new architecture for the square root (SQRT) carry select adder (CSLA) using half-sum generation (HSG), half-carry generation (HCG), full-sum generation (FSG) and full-carry generation (FCG) blocks. The proposed design contains N-bit architecture, and comparative results are considered for 8-bit, 16-bit and 32-bit combinations. All the designs are implemented in the Xilinx ISE environment and the results show that better area, power, and delay performance compared to the state of art methods.

An integrated PMU architecture for power system applications

Time synchronized phasors obtained using Phasor Measurement Units (PMU) spread across wide areas have revolutionized power system monitoring and control. These synchronized measurements must be accurate and fast in order to comply with the latest IEEE standards for synchrophasor measurements. The speed at which a PMU provides an output depends on the group delay associated with that PMU and the permissible group delay in-turn decides the utility of a PMU for either control or measurement application. Based on the group delay compensation techniques, in the literature, two individual types of PMUs, such as causal and non-causal PMUs have been introduced. This paper presents an approach where both causal and non-causal PMUs are combined in an integrated PMU architecture. This method not only illustrates the group delay performance of two PMUs in a single module, but also can be used for multiple functions. In this environment several PMU algorithms have been compared with respect to their group delays and their effect on the response time. Application of the integrated PMU architecture to a four-machine 10-bus power system has been demonstrated using a six-input PMU with three-phase voltage and current signals as inputs. Different causal compensation schemes are introduced due to the availability of voltage and current-based frequency and ROCOF signals. Impact of these compensation schemes on PMU accuracy is evaluated through the Total Vector Error (TVE) index. The influence of these compensation schemes on measurements like power and impedance is also investigated. Finally, outputs from the integrated PMU architecture are fed into a Power System Stabilizer (PSS) to control the small-signal stability performance of a power system during dynamic conditions.

A CS-Based Grant-Free Media Access Scheme for NOMA-Based Industrial IoTs with Location Awareness

Grant-free media access is vital for applications in Industrial IoTs (IIoTs), where stringent delays are required. Recently, due to the capability of supporting parallel receptions, Non-Orthogonal Multiple Access (NOMA) has gained research interests in IIoTs. Obviously, combining them organically is beneficial for enhancing the delay performances. In this paper, for a typical convergecast wireless network where its data sink is NOMA-based, we propose a grant-free MAC (Media Access Contention) scheme based on Compressive Sensing in Busy Tone Channel (CSiBTC), by exploiting the transmission sparsity in IIoTs. First, a to-be transmitter acquires the identities of active transmitters with the proposed CSiBTC scheme completely by itself. Two construction methods for CSiBTC are proposed for two distinct application scenarios respectively. Then, given the locations of all wireless sensors and the data sink in the network, the to-be transmitter can find out if it is eligible for starting its transmission without impairing the on-going transmissions. The scheme is grant-free and makes the most use of the parallel reception capability of NOMA, and therefore both the delay performance and throughput performance can be improved with respect to the general CS-based MAC. Performance evaluations also strongly support the above conclusions.

Effects of Hazmat Train Speed Restrictions on Train Delay Performance and Railroad Line Capacity: Comparative Study with Two Railway Simulation Tools

In response to multiple derailments involving hazmat trains, in early February 2020 Transport Canada released ministerial order (MO) 20-02, imposing speed restrictions of 20 to 25 mph on trains transporting a sufficient quantity of hazardous material. Since much of the North American freight network is used by multiple train types, the extreme speed heterogeneity created by this mandate substantially reduced train performance. Although this order was replaced within 2 weeks by new speed restrictions that were in turn replaced in May, MO 20-02 introduced the most extreme levels of train speed heterogeneity. The research team investigated the corresponding capacity effects to better understand the effects of train speed heterogeneity at low speed and inform agencies on future speed restrictions in this range. Using Rail Traffic Controller and General Train Movement Simulator, we quantitatively investigated the capacity loss from these speed restrictions and found that MO 20-02 can double or triple average train delay and lead to mainline capacity loss in excess of 60% on a representative single-track mainline.